STLC5432 datasheet(20/46 Pages) STMICROELECTRONICS

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9.24 CR2: Configuration Register 2

DOHZ RDS1 RDS0 POL

After Reset = 80H

Transparent Mode.

For the transmitter, when this bit is at 1, the

bit stream received on DIN pin is introduced

directly into the Binary HDB3 encoder.

In this case, FSX (Frame Synchronization

Signal) from the pin is not used by the

transmitterand Time Slot 0 is not known by the

transmitter. The logical result is the same if the

bit stream is introduced onto BXDI pin at

2048 kb/s.

For the receiver, when TM is at ”1”, every

bit received from HDB3-BIN decoder is

connected onto DOUT through the Elastic

Memory. The synchronization is researched

and indicated by the different alarm registers

but DOUT pin delivers the received bit

stream without taking into account the result

of the synchronization.

BRDO and RCLO pins provide the bit stream

received from the decoder.

PRBS Type to be transmitted.

When the generator of Pseudo Random

Binary Sequency is validated (SGV =1):

if NX = 0, the length of sequence is 2*15-1

bits

if NX = 1, the length of sequence is 2*11-1

bits.

PRBS type received.

When the Analyzer of Pseudo Random

Binary Sequence is validated (SAV = 1):

If NR = 0, the length of sequence received

is 2*15-1 bits (O.151)

If NR = 1, the length of sequence received

is 2*11-1 bits (O.152)

POL

Fault Counter Register Polling.

POL = 1

FCR1 and FCR2 registers or ECR1

andECR2 registers or PCR1 and

PCR2 registers are read by the

microprocessor (Polling Mode).

First FCR1, or ECR1, or PRC1, is

read then FCR2, or ECR2, or PRC2,

mandatory. The contents of a pair of

registers indicate the number of faults

occured from the last reading of this

pair of register.

POL = 0

The two pairs of registers indicate

the number of faults occured during

the second which is passed just

before InterruptSC.

9.23 CR1: Configuration Register 1

MERA LTM 8KCR MCR1 MCR0 SELEX SELER

After Reset = 84H

SELER Selection of an external signal side

receiver.

When SELER=1, the internal binary data

signal and its clock associated are replaced

by the external binary data signal and its

clock associated (respectively BRDI and

RCLI).

SELEX Selection of an external signal side

transmitter.

When SELEX = 1, the internal

binary data signal is replaced by the

external data signal BXDI.

MCR0/1 HCR Frequency

HCR pin delivers a square wave

MCR1

MCR0

HCR Frequency in kHz

2048

4096

8192

8KCR 8kHz Clock Received

8KCR = 1

LCR pin delivers a square wave at

8kHz (Low clock received)

8KCR0 = 0

LCR pindelivers asquarewaveat 4kHz

LTM

Line Termination Mode

When LTM is at ”1”, the jitter filter is not

validated. HCR and LCR pins deliver

signals at a submultiple frequency of the

frequency applied to XTAL1 pin.

HCR frequency is in accordance with

MCR0/1 and LCR frequencyis in accordance

with 8KCR.

When LTM is at ”0”, jitter filter is validated

andMCR and LCR pins deliver cloks issued

from DPLL in accordance with MCR0/1

and 8KCR.

MERA Mask Error rate

MERA = 0

WER bit (Error Rate over threshold)

is taken into account to transmit A

bit and to force to 1 the DOUTpin.

MERA = 1

WER bit is ignored by A bit trans-

mission and DOUT pin.

STLC5432

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