STLC5432 datasheet(28/46 Pages) STMICROELECTRONICS

28 / 46 page

LINE STATE

REGISTERS

RECEIVING

ALARMS

DETECTED

ALARMS

TRANSMITTED

ODD TS0

BIT 3

LOS

AIS

915

LOF

WER

CAR1

COMPLEM.

ALARM

ALR

ALARMS

(TSOXR)

AE Bit

MERA

(CR1)

Bit 0

Bit 1

Bit 2

Bit 3

Bit 0

Bit 5

and

D93TL050B

Figure 5: Main Alarm Processing

SA pin: 0V

SA pin: 5V

Serial Interface

P0 + P1 = 0

Parallel Interface: P0 + P1 # 0

Stand Alone

During

Time Slot 0:

IF TSOE = 0 (CR5)

During Time Slot 0:

Dout pin is High Z.

IF TSOE = 1

During Time Slot 0:

Dout pin delivers consecutively:

Dout pin

delivers

messages

and

Din pin

receives

messages

ODD

SKIP

SLC

Sa4R

Sa5R

Sa6R

Sa7R

Sa8R

ODD = 1 The contents of 31 Time Slots is related to

odd frame received from the line.

ODD = 0 The contents of 31 Time Slots is related to

even frame received from the line. (See Figure 6a).

Din pin receives eight bits:

Sa4E

Sa5E

Sa6E

Sa7E

Sa8E

During Time Slot 0:

Dout pin delivers eight alarms

SLC

SKIP

MFNR

LOF

AIS

LOS

Din pin is ignored during Time Slot 0

D93TL051E

Figure 6: DIN and DOUT During Time slot 0.

STLC5432

28/46

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