STLC5432 datasheet(24/46 Pages) STMICROELECTRONICS

24 / 46 page

Transmitter side:

SaT fixs the number of consencutive

transmissions of Sa61 to Sa64 bits onto

the line before resetting WT (Sa6XR register).

See definition of WT bit in chapter 9.19

OSCD Oscillator Disabled

OSCD = 1, The clock pulse applied to

XTAL1 input pin comes from an external

generator. The internal oscillator is disabled

to reduce power consumption.

XTAL2 pin has to be left open.

OSCD = 0, The two pins of a crystal are

connectedto XTAL1 pin and XTAL2 pin in

accordance with the application schematic

andthe internal oscillator is enabled.

POLSa = 1: Each bit of TS0RR register is reset

after a reading cycle from microprocessor

except if the condition to set the bit at ”1” is

still present.

POLSa = 0: Each bit of TS0RR Register is always

reset after a reading cycle from microproces-

sor. (see also SP bit of CR8 Register).

9.29 CR7 Configuration Register 7

AMI

Sa81 Sa80 Sa71 Sa70 Sa61 Sa60

After Reset = 80H

Sa60/Sa61

Sa61 Sa60

For Subchannel Sa6

in Transmission,

the source is:

For Subchannel

Sa6 in Reception,

the destination is:

Bit Sa6X of TS0XR

Sa60 and Sa61 are

not taken into

account: TS0RR

Sa6R and DOUT pin

delivers Bit Sa6R

Bit Sa6X of DIN

received during TS0

Contents of Sa6XR

Sa6RR Register

Reserved Code: Do not use

Sa70/Sa71:same definition as Sa40/Sa41.

Sa80/Sa81:same definition as Sa40/Sa41.

AMI

Alternate Mark Inversion.

AMI = 0, select HDB3 code on the line.

AMI = 1, select AMI code on the line.

9.30 CR8 Configuration Register 8

FILT

Sa4P Sa5P Sa6P Sa7P Sa8P

After Reset = FFH

Sa8P

Sa8 Bit Polarity. This bit is taken into

account if SP =1.

Sa8P =1, Sa8R bit (of TS0RR Register) is

set at ”1”, in accordance with FILT,

when Sa8 bit received from the line

goes from ”0” to ”1”.

Sa8P =0, Sa8R bit (of TS0RR Register) is

set at ”1”, in accordance with FILT,

when Sa8 bit received from the line

goes from ”1” to ”0”.

Sa7P to Sa4P Same definition as Sa8P

Single Polarity

SP =1, Sa8P to Sa4P and POLSa (CR6

account. Sa8 to Sa4 (changing

state) received from the line are

stored into TS0RR Register in

accordance with FILT. When

TS0RR Register is read by the

microprocessor, TS0RR is put to 0

in accordance with POLSa bit (CR6

SP = 0, Sa8P to Sa4P and POLSa bits are

not taken into account.

Sa8 to Sa4 bits received from the

line are stored into TS0RR Register

in accordance with FILT. When

TS0RR Register is read by the

microprocessor, TS0RR keeps its

contents.

FILT

FILTERING

Receiver side:

FILT = 1 and SP = 1,

Sa8R to Sa4R bits of TS0RR

if a new state has been received

three times consecutively from

each channelSa8 to Sa4 processed

separately one by one. A TS0R

interrupt is generated.

FILT = 0 and SP = 1,

Sa8R to Sa4R bits of TS0RR

a new state has been received

twice consecutively from each

channel Sa8 to Sa4 processed

separately one by one. A TS0R

interrupt is generated.

FILT = 1 and SP = 0,

Sa8 to Sa4 bits received from the

line and processed independently

are stored into TS0RR Register

if one new bit has been received

three times identically at least. A

TS0R interrupt is generated.

FILT = 0 and SP = 0,

Sa8 to Sa4 bits received from the

line are stored into TS0RR Register

each 250ms without processing. A

TS0R interrupt is generated.

Transmitter side:

See TS0XR register definition chapter 9.18.

STLC5432

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