STLC5432 datasheet(25/46 Pages) STMICROELECTRONICS

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9.33 TCR2: Test Configuration Register 2

SAV

ATS5 ATS4 ATS3 ATS2 ATS1 ATS0

After Reset = 80H

ATS0 to ATS5 Time Slot associated to Analyzer.

These 6 bits indicate Time Slot(s)

selected to receive the Pseudo

Random Binary

Sequence (PRBS). The internal analyzer

checks the sequence.

SAV

Sequence Analyzer Validated.

When SAV is at ”1”, the analyzer is

validated and the counter ECR1-ECR2

(14 bits) is associated to analyzer. The

length of PRBS is in accordance with NR

bit. After the sequence is recovered by the

analyzer. PRSR is set at ”1”

(Complementry Alarm

the number of faults received.

ATS5

ATS4

ATS3

ATS2

GTS1

GTS0

Time Slot(s) selected to receive PRBS

All the Time Slots except TS0

All the Time Slots including TS0

Not use

000

TS1

000

TS2

↓↓

↓

TS30

TS31

9.32 TCR1: Test Configuration Register 1

SGV GTS5 GTS4 GTS3 GTS2 GTS1 GTS0

After Reset = 80H

GTS0 to GTS5 Time Slot associated to generator.

These 6 bits indicate Time Slot(s)

selected to transmit the Pseudo

Random Binary

Sequence(PRBS) provided by the internal

generator (see Table).

SGV

Sequence Generator Validated.

When SGV is at ”1”, the generator provides

Pseudo Random Binary Sequence in

accordance with NX bit. When SGV is at 0,

the generator is not validated.

GTS5

GTS4

GTS3

GTS2

GTS1

GTS0

Time Slot(s) selected to transmit

PRBS

000000

All the Time Slots except TS0

All the Time Slots including TS0

100000

Not use

100001

TS1

100010

TS2

↓

↓↓↓

↓↓

↓

111110

TS30

111111

TS31

STLC5432

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