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STLC5432 数据表(PDF) 16 Page - STMicroelectronics |
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STLC5432 数据表(HTML) 16 Page - STMicroelectronics |
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16 / 46 page  When a bit of this register is at ”1”, the CAR1 Register bit which has the same number is masked. The CAR1 bit which is masked do not generate an interrupt. 9.6 CAR2: Complementary Alarm Register 2 70 1 PRSL PRSR MFNR MFR 0 SLC SKIP After Reset = 80H SKIP SKIP. After frame recovery, this bit is at ”1” when an entire frame (32 words) has been ignored or has been repeated two times onto DOUT. SLC Slow Local Clock. This bit does not generate interrupt. When the value of this bit is 0, local clock is faster than the remote clock. When the value is ”1”, local clock is slower than the remote clock (an entire frame has been ignored). MFR Multiframe recovered within 400 ms. After reframe time, if the multiframe is recovered within 400 ms, MFR is set to ”1”. MFNR Multiframe Not recovered within 500 ms. After reframe time, the circuit researches the multiframe during 500 milliseconds. After this time, if the multiframe has not been recovered, MFNR is set at ”1”. Then the circuit is activated with the frame recovery only, and the AX bit (bit 3 of the odd Time Slot Zero transmitted) is set at ”0”. PRSR Pseudo Random Sequence Recovered. When the PRS analyzer is validated (SAV = 1), PRSR bit is set at ”1” if the synchro- nization is performed. PRSL Pseudo Random Sequence Lost. PRSL, this bit is set to ”1” when PCR1/2 (PRS Counter Register) has reached 2 14 detected faults. 9.7 CAMR2: Complementary Alarm Mask Register 2 70 1 MPRSL MPRSR MMFNR MMFR Nu 1 MSKIP After Reset = FFH This register can be read or written. Bits: MMFNR, MMFR and MSKIP mask respectively bit MFNR, MFR and SKIP when they are at ”1”. 9.8 FCR1: Fault Counter Register 1 70 1 F6 F5 F4 F3F2F1F0 After Reset = 80H F0/6 7 less significant bits of the FCR counter. 9.9 FCR2: Fault Counter Register 2 70 1 F13 F12 F11 F10 F9 F8 F7 After Reset = 80H F7/13 7 most significant bits of the FCR counter. If POL bit of CR2 register is at ”0”, the value of 14 bits fault counter is loaded into these registers each second. If POL = 1, the registers are reset- ted after each access. (POL indicates the differ- ence between polling mode and interrupt mode, see also CR2 register). When the multiframe has not been recovered within 400ms (MFNR = 1), these two registers in- dicate the number of errored bits of Frame Align- ment Signal received over one second period. When the multiframe is recovered, these two reg- isters indicate the number of errored CRC blocks received over one second period. 9.10 ECR1: E Bit Counter Register 1 70 1 E6 E5E4 E3E2E1E0 After Reset = 80H E 0/6 7 less significant bits of ECR counter 9.11 ECR2: E Bit Counter Register 2 70 1 E13 E12 E11 E10 E9 E8 E7 After Reset = 80H E 7/13 7 most significant bits of the ECR counter . ECR1 and ECR2 are two registers associated to ECR counter. Each second, the value of the counter is loaded into these register (POL = 0). When the multiframe is recovered, these two reg- isters indicate the number of errored E bits re- ceived over 1 second period. STLC5432 16/46 |
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