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STLC5432 数据表(PDF) 23 Page - STMicroelectronics |
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STLC5432 数据表(HTML) 23 Page - STMicroelectronics |
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23 / 46 page  9.27 CR5 Configuration Register 5 70 1 TS0E APD NMF HCRD DPIS CENTER FROZ After Reset = 80H FROZ Frozen DPLL. FROZ = 1, the DPLL is immediately frozen. Id est: DPLL retains its phase and its frequency while FROZ is at ”1”. CENTER Crystal Oscillator Rference. CENTER = 1, DPLL is synchronised by the Crystal Oscillator. CENTER = 0, DPLL is synchronised by the clock recovered from the line or by the signal applied to DPLL INPUT PIN (DPI) in accordance with DPIS. DPIS DPLL Input Selection. DPIS = 1, internal DPLL input receives the signal applied to DPLL INPUT PIN (DPI) DPIS = 0, internal DPLL input receives the signal recovered from the line. HCRD HCR Disabled. HCRD = 1, HCR pin is high impedance HCRD = 0, HCR pin is low impedance. NMF No Multiframe. NMF = 1 the multiframe is not transmitted, only the Frame Alignement Signal (FAS) is transmitted on the line duringthe time slot 0. The receiver is not concerned by this bit. NMF = 0 the multiframe (MFAS) is trans- mitted with the CRC4, the Frame Aligne- ment Signal (FAS) is transmitted in accord- ance with G.704. APD Alarm Pattern on DOUT. When this bit is ”1”, DOUT Pin delivers Auxiliary Pattern: (0-1-0-1-0-1...). TS0E DOUT enabled during Time Slot Zero. In serial microprocessor mode, this bit is not significant: in this case Time Slot Zero is used to exchange data between the device and the remote serial interface microprocessor. In parallel microprocessor mode,TS0E bit is taken into account: TS0E =1. Sa4R to Sa8R bits of the TS0RR Register are transmitted onto DOUT during the time Slot Zero. The bits 1 to 3 of this same time Slot Zero are ODD, SKIP, SLC. - When ODD = 1, the contents of Time Slot 1 to 31 are relative to the contents of odd frame received from the line. - When ODD = 0, the contents of Time Slot 1 to 31 are relative to the content s of even frame received from the line. If the sinchronisation is lost or if the error rate is over the programmed threshold, the DOUT pin is set at ”1”. The bits 4 to 8 of the incoming time Slot Zero (DIN pin) are transmitted onto the line in accordance with CR6 and CR7 Registers. Bits 1 to 3 are ignored. TS0E = 0. DOUT is high impedance during the time Slot Zero. Incoming bits on DIN pin are ignored during Time Slot Zero. 9.28 CR6 Configuration Register 6 70 1 POLSa OSCD SaT Sa51 Sa50 Sa41 Sa40 After Reset = 80H Sa40/Sa41 Sa41 Sa40 For Subchannel Sa4 in Transmission, the source is: For Subchannel Sa4 in Reception, the destination is: 0 0 Bit Sa4X of TS0XR Register TS0RR Register receives Bit Sa4R and DOUT pin delivers Bit Sa4R. 0 1 Bit Sa4X of DIN received during TS0 1 0 Reserved Code: Do not use 1 1 Reserved Code: Do not use Sa50/Sa51 Sa51 Sa50 For Subchannel Sa5 in Transmission, the source is: For Subchannel Sa5 in Reception, the destination is: 0 0 Bit Sa5X of TS0XR Register TS0RR Register receives Bit Sa5R and DOUT pin delivers Bit Sa5R. 0 1 Bit Sa5X of DIN received during TS0 1 0 Reserved Code: Do not use 1 1 Reserved Code: Do not use SaT Same Bits Three times. SaT = 1: if a new value for the Sa5R, Sa61R, Sa62R, Sa63R and Sa64R bits has been received three times identical, these bits are loaded into Sa6RR register and a Sa6R interrupt is generated. SaT = 0: each millisecond the Sa5R, Sa61R, Sa62R, Sa63R and Sa64R bits are loaded into Sa6RR register and a Sa6R interrupt is generated. STLC5432 23/46 |
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