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STLC5466 数据表(PDF) 107 Page - STMicroelectronics |
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STLC5466 数据表(HTML) 107 Page - STMicroelectronics |
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107 / 130 page  107/130 STLC5466 2.2 TDM synchronization Figure 2-2: Sychronization signals received by the Multi-HDLC Parameter T min T typ T max Unit t1 DCLK Clock Period if 4096 kHz (3072) DCLK Clock Period if 2048 kHz (1536) Id CLOCKA or B (T min) 244 (325) 488 (651) Id CLOCKA or B (T max) ns ns t2 Delay between CLOCK A or B and DCLK (30pF) 530 ns t3 Set up time FS/DCLK 20 t1-20 ns t4 Hold time FS/DCLK 20 ns t5 Duration FS 244 (325) 125 000-244 ns t6 DCLK to data 50 pF DCLK to data 100 pF 50 100 ns ns t7 Set up time data/DCLK 20 ns t7 Hold time data/DCLK 20 ns t8 Set up Echo/DCLK (rising edge) 155 ns t9 Hold time Echo/DCLK (rising edge) 205 ns The four Multiplex Configuration Registers are at zero (no delay between FS and Multiplexes). DCLK delivered by DIN 0/8 FS received by DOUT 0/7, CB Bit0, Time Slot 0 the Multi-HDLC the Multi-HDLC Bit7, Time Slot 31 t1 t3 t4 t5 t6 t7 t7 t2 CLOCK A (or B) Echo t8 t9 |
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