 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
STLC5466 数据表(PDF) 108 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
STLC5466 数据表(HTML) 108 Page - STMicroelectronics |
|
|
108 / 130 page  STLC5466 108/130 2.3 GCI interface Figure 2-3: Sychronization signals delivered by the Multi-HDLC Parameter T min T typical T max t1 DCLK Clock Period if 4096 kHz (3072) DCLK Clock Period if 2048 kHz (1536) Id CLOCKA or B (T min) 244 (325) 488 (651) Id CLOCKA or B (T max) t3 DCLK to FSCG 20 t5 Duration FS 244 125000-244 t6 DCLK to data 50 pF DCLK to data 100 pF 50 100 t7 Set up time data/DCLK 20 t7 Hold time data/DCLK 20 The four Multiplex Configuration Registers are at zero (no delay between FS and Multiplexes). DCLK delivered DIN 0/8 FSCG delivered DOUT 0/7, CB Bit0, Time Slot 0 by the Multi-HDLC by the Multi-HDLC CH 0 CH 1 CH7 DIN4/5 125ms MON D C/I AE B1 B2 DOUT4/5 FS received by the Multi-HDLC t3 t3 t6 t7 t7 t1 If FSCG connected to FS |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
