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STLC5466 数据表(PDF) 110 Page - STMicroelectronics

部件名 STLC5466
功能描述  64 CHANNEL-MULTI HDLC WITH N X 64KB/S SWITCHING MATRIX ASSOCIATED
PDF  130 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STLC5466 数据表(HTML) 110 Page - STMicroelectronics

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3
SDRAM MEMORY TIMING
Figure 3-1: Signals exchanged between SDRAM controller and SDRAM
Parameter
T min
T max
Unit
T
1/T= 33, 50 or 66 MHz
ts
Data in set up time
3
ns
th
Data in Hold time
2
ns
td
Delay between rising edge of CLK and
each signal delivered by the Multi-HDLC
CL= 5 pF (Vdd = 3.3V ± 5% Temp 0 to 70°C)
CL= 30 pF
CL= 50 pF
3
3
3
10
12
20
ns
ns
ns
Signals provided by the Multi-HDLC and received from the Synchronous Dynamic Memory
MCLK is an input.
Clock provided by
an external clock
generation
Input:
Data from SDRAM
Output:
signals
to SDRAM
ts
th
2.0
1.4
0.8
2.0
1.4
0.8
td
T



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