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Numonyx™ Wireless Flash Memory (W18)

Datasheet

November 2007

Order Number: 290701-18

Numonyx™ Wireless Flash Memory (W18)

9.0

Bus Operations Overview

This section provides an overview of device bus operations. The Numonyx™ Wireless

Flash Memory (W18) family includes an on-chip WSM to manage block erase and

program algorithms. Its Command User Interface (CUI) allows minimal processor

overhead with RAM-like interface timings. Device commands are written to the CUI

using standard microprocessor timings.

9.1

Bus Operations

Bus cycles to/from the W18 device conform to standard microprocessor bus operations.

Table 21 summarizes the bus operations and the logic levels that must be applied to

the device’s control signal inputs.

9.1.1

Reads

Device read operations are performed by placing the desired address on A[22:0] and

asserting CE# and OE#. ADV# must be low, and WE# and RST# must be high. All read

operations are independent of the voltage level on VPP.

CE#-low selects the device and enables its internal circuits. OE#-low or WE#-low

determine whether DQ[15:0] are outputs or inputs, respectively. OE# and WE# must

not be low at the same time - indeterminate device operation will result.

In asynchronous-page mode, the rising edge of ADV# can be used to latch the address.

If only asynchronous read mode is used, ADV# can be tied to ground. CLK is not used

in asynchronous-page mode and should be tied high.

In synchronous-burst mode, ADV# is used to latch the initial address - either on the

rising edge of ADV# or the rising (or falling) edge of CLK with ADV# low, whichever

occurs first. CLK is used in synchronous-burst mode to increment the internal address

counter, and to output read data on DQ[15:0].

Each device partition can be placed in any of several read states:

• Read Array: Returns flash array data from the addressed location.

• Read Identifier (ID): Returns manufacturer ID and device ID codes, block lock

status, and protection register data. Read Identifier information can be accessed

from any 4-Mbit partition base address.

Table 21: Bus Operations Summary

Bus Operation

RST#

CLK

ADV#

CE#

OE#

WE#

WAIT

DQ[15:0

]

Notes

Read

Asynchronous

VIH

Asserted

Output

Synchronous

VIH

Running

Driven

Output

Burst Suspend

VIH

Halted

Active

Output

Write

VIH

Asserted

Input

Output Disable

VIH

Asserted

High-Z

Standby

VIH

High-Z

Reset

VIL

High-Z

3,4

Notes:

WAIT is only valid during synchronous array-read operations.

Refer to the

Table 23, “Bus Cycle Definitions” on page 52 for valid DQ[15:0] during a write

operation.

X = Don’t Care (H or L).

RST# must be at VSS ± 0.2 V to meet the maximum specified power-down current.

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