PC48F4400PLVB0 datasheet(55/102 Pages) NUMONYX

55 / 102 page

November 2007

Datasheet

Order Number: 290701-18

Numonyx™ Wireless Flash Memory (W18)

10.0

Read Operations

The device supports two read modes - asynchronous page and synchronous burst

mode. Asynchronous page mode is the default read mode after device power-up or a

reset. The Read Configuration Register (RCR) must be configured to enable

synchronous burst reads of the flash memory array (see Section 14.0, “Set Read

Configuration Register” on page 78).

Each partition of the device can be in any of four read states: Read Array, Read

Identifier, Read Status or CFI Query. Upon power-up, or after a reset, all partitions of

the device default to the Read Array state. To change a partition’s read state, the

appropriate read command must be written to the device (see Section 9.2, “Device

Commands” on page 50).

The following sections describe device read modes and read states in detail.

10.1

Asynchronous Page Read Mode

Following a device power-up or reset, asynchronous page mode is the default read

mode and all partitions are set to Read Array. However, to perform array reads after

any other device operation (e.g. write operation), the Read Array command must be

issued in order to read from the flash memory array.

Note:

Asynchronous page-mode reads can only be performed when Read Configuration

page 78).

To perform an asynchronous page mode read, an address is driven onto A[MAX:0], and

CE#, OE# and ADV# are asserted. WE# and RST# must be deasserted. WAIT is

asserted during asynchronous page mode. ADV# can be driven high to latch the

address, or it must be held low throughout the read cycle. CLK is not used for

asynchronous page-mode reads, and is ignored. If only asynchronous reads are to be

performed, CLK should be tied to a valid VIH level, WAIT signal can be floated and

ADV# must be tied to ground. Array data is driven onto DQ[15:0] after an initial access

time tAVQV delay. (see Section 7.0, “AC Characteristics” on page 26).

In asynchronous page mode, four data words are “sensed” simultaneously from the flash

memory array and loaded into an internal page buffer. The buffer word corresponding

to the initial address on A[MAX:0] is driven onto DQ[15:0] after the initial access delay.

Address bits A[MAX:2] select the 4-word page. Address bits A[1:0] determine which

word of the 4-word page is output from the data buffer at any given time.

10.2

Synchronous Burst Read Mode

Read Configuration Register bits RCR[15:0] must be set before synchronous burst

operation can be performed. Synchronous burst mode can be performed for both array

and non-array reads such as Read ID, Read Status or Read Query (See for details).

Synchronous burst mode outputs 4, 8, 16, or . To perform a synchronous burst- read, an

initial address is driven onto A[MAX:0], and CE# and OE# are asserted. WE# and

RST# must be deasserted. ADV# is asserted, and then deasserted to latch the address.

Alternately, ADV# can remain asserted throughout the burst access, in which case the

address is latched on the next valid CLK edge after ADV# is asserted. See Section 14.0,

“Set Read Configuration Register” on page 78

During synchronous array and non-array read modes, the first word is output from the

data buffer on the next valid CLK edge after the initial access latency delay (see Section

14.2, “First Access Latency Count (RCR[13:11])” on page 79). Subsequent data is

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