PC48F4400PLVB0 datasheet(82/102 Pages) NUMONYX

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Numonyx™ Wireless Flash Memory (W18)

Datasheet

November 2007

Order Number: 290701-18

Numonyx™ Wireless Flash Memory (W18)

14.5

Data Hold (RCR[9])

The Data Output Configuration (DOC) bit (RCR[9]) determines whether a data word

remains valid on the data bus for one or two clock cycles. The processor’s minimum

data set-up time and the flash memory’s clock-to-data output delay determine whether

one or two clocks are needed.

A DOC set at 1-clock data hold corresponds to a 1-clock data cycle; a DOC set at 2-

clock data hold corresponds to a 2-clock data cycle. The setting of this configuration bit

depends on the system and CPU characteristics. For clarification, see Figure 39, “Data

Output Configuration with WAIT Signal Delay” on page 83.

A method for determining this configuration setting is shown below.

To set the device at 1-clock data hold for subsequent reads, the following condition

must be satisfied:

tCHQV (ns) + tDATA (ns) ≤ One CLK Period (ns)

As an example, use a clock frequency of 66 MHz and a clock period of 15 ns. Assume

the data output hold time is one clock. Apply this data to the formula above for the

subsequent reads:

11 ns + 4 ns ≤ 15 ns

This equation is satisfied, and data output will be available and valid at every clock

period. If tDATA is long, hold for two cycles.

During page-mode reads, the initial access time can be determined by the formula:

tADD-DELAY (ns) + tDATA (ns) + tAVQV (ns)

Subsequent reads in page mode are defined by:

tAPA (ns) + tDATA (ns)

(minimum time)

Table 34: WAIT Signal Conditions

CONDITION

WAIT

CE# = VIH

CE# = VIL

Tri-State

Active

OE#

No-Effect

Synchronous Array Read

Active

Synchronous Non-Array Read

Asserted

All Asynchronous Read and all Write

Asserted

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