PC48F4400PLVB0 datasheet(50/102 Pages) NUMONYX

50 / 102 page

Numonyx™ Wireless Flash Memory (W18)

Datasheet

November 2007

Order Number: 290701-18

Numonyx™ Wireless Flash Memory (W18)

9.1.5

Standby

De-asserting CE# deselects the device and places it in standby mode, substantially

reducing device power consumption. In standby mode, outputs are placed in a high-

impedance state independent of OE#. If deselected during a program or erase

algorithm, the device shall consume active power until the program or erase operation

completes.

9.1.6

Reset

The device enters a reset mode when RST# is asserted. In reset mode, internal

circuitry is turned off and outputs are placed in a high-impedance state.

After returning from reset, a time tPHQV is required until outputs are valid, and a delay

(tPHWV) is required before a write sequence can be initiated. After this wake-up

interval, normal operation is restored. The device defaults to read-array mode, the

Status Register is set to 80h, and the Configuration Register defaults to asynchronous

page-mode reads.

If RST# is asserted during an erase or program operation, the operation aborts and the

memory contents at the aborted block or address are invalid. See Figure 19, “Reset

Operations Waveforms” on page 44 for detailed information regarding reset timings.

Like any automated device, it is important to assert RST# during system reset. When

the system comes out of reset, the processor expects to read from the flash memory

array. Automated flash memories provide status information when read during program

or erase operations. If a CPU reset occurs with no flash memory reset, proper CPU

initialization may not occur because the flash memory may be providing status

information instead of array data. Numonyx flash memories allow proper CPU

initialization following a system reset through the use of the RST# input. In this

application, RST# is controlled by the same CPU reset signal.

9.2

Device Commands

The device’s on-chip WSM manages erase and program algorithms. This local CPU

(WSM) controls the device’s in-system read, program, and erase operations. Bus cycles

to or from the flash memory conform to standard microprocessor bus cycles. RST#,

CE#, OE#, WE#, and ADV# control signals dictate data flow into and out of the device.

WAIT informs the CPU of valid data during burst reads. Table 21, “Bus Operations

Summary” on page 48 summarizes bus operations.

Device operations are selected by writing specific commands into the device’s CUI.

Table 22, “Command Codes and Descriptions” on page 51 lists all possible command

codes and descriptions. Table 23, “Bus Cycle Definitions” on page 52 lists command

definitions. Because commands are partition-specific, it is important to issue write

commands within the target address range.

PC48F4400PLVB0 数据表(PDF) 50 Page - Numonyx B.V

PC48F4400PLVB0 数据表(HTML) 50 Page - Numonyx B.V

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载