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ORCA ORSPI4 Data Sheet

Status

I/Os

SPIA_TX32_PORT_ID[7:0]

Core

→FPGA

Port number of the currently serviced SPI4 data port. The value can either

be the actual SPI4 value or a programmed user value. Further details are

provided in the TX Calendar Control Logic description.

SPIA_TX32_STAT[1:0]

Core

→FPGA

Status of the SPI4 port currently being serviced. These signals can be

used in conjunction with the SPIA_TX32_PORT_ID signal to police trans-

mit trafﬁc congestion for a particular SPI4 port.

SPIA_TX32_BURST_VAL[3:0]

Core

→FPGA

Indicates the number of SPI4 cycles for which the currently active port will

be serviced. Each cycle indicates an attempt to read 128 bits of data from

the respective FIFO partition.

ATREFCLK_F

Core

→FPGA

Transmit reference clock. This clock signal is 1/4th the SPI4 clock. This sig-

nal can be used to synchronize FPGA application logic to the FPSC logic.

SPIA_TREFCLK_X8

FPGA

→ Core

Quarter-rate Transmit reference clock. This FPGA-sourced clock reference

must be 2x the desired Transmit SPI4 line clock rate. When not operating

the Transmit SPI4 core in Quarter-rate mode, this signal should be tied off.

Ex: For a 100 MHz Transmit SPI4 line clock, SPIA_TREFCLK_X8 from the

FPGA must be 200 MHz.

Misc.

I/Os

SPI_SATM_A

FPGA

→ Core ‘0’ - Incoming ATSCLK is assumed to be edge-aligned with the data and

centered to the data eye within the chip.

‘1’ - Incoming ATSCLK is assumed to be skewed with respect to the data

off-chip.

Table 2. SPIA Core Transmit FPGA Interface in 32-Bit Mode (Continued)

DPRAM

FPGA Interface I/Os

Direction

From/To

Description

Note: For SPIB replace A with B

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