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ORCA ORSPI4 Data Sheet

• If training is to be used, the user must also conﬁgure the 16-bit TX_ALPHA variable to indicate the number of

times the training pattern is to be repeated. By default the value is 0x0000 which disables the training pattern.

If the number of Bytes within the training sequences do not ﬁll entire SPI4 Burst Cycle, the unused Byte ﬁelds will

be padded with Idle data in order to keep the training sequences aligned on 16 Byte boundaries.

Calendar Programming

On a SPI4 link, FIFO status information is received periodically over the status link (TSTAT bus on the SPI4 inter-

face) from the device that sources data. Calendar is a means by which the SPI4 link conveys information to the TX

data source about the availability of buffer space in the RX FIFOs that receive data from that data source. A calen-

dar is a sequence of status messages that:

• Provides information on the buffer space for a port or trafﬁc ﬂow.

• Allows user to allocate bandwidth for a port or ﬂow depending on the overall trafﬁc characteristics.

The SPI4 status channel operates at 1/8th the SPI4 data rate, which is reasonable because data is always sent in

16-byte bursts. Thus, the fastest status update can be expected once in every 8 data clock cycles. For a given port,

the frequency with which its status is reported to the far-end transmitter source depends on the allocated band-

width for the port. It is imperative that the transmitter and receiver devices are programmed with identical calendar

sequences. The following examples illustrate this:

Suppose a channelized STS-48 has three STS-12 ports and four STS-3 ports (channels), each STS-12 port

should have four times the bandwidth of an STS-3 port and 12 times the bandwidth of an STS-1 port within a single

calendar cycle. The ﬁrst step is to map each port to an 8-bit Port ID (address) as shown in Table 23

Table 10. Port ID Mapping

The calendar sequence is as follows:

A1, A2, A3, B1, A1, A2, A3, B2, A1, A2, A3, B3, A1, A2, A3, B4

The number of calendar entries is thus 16. This calendar sequence is programmed in the transmit calendar mem-

ory as follows:

• This example uses the main calendar. The calendar memory is selected by setting the TX_CAL_MEM_SEL bit

(address 30917 in SPIA and address 30A17 in SPIB) to ‘1’.

• Writes are done to addresses 0x31000 - 0x3100F. This will correspond to entries 0x00 - 0x0F in the calendar

memory. This is shown in Table 11. Note that the main calendar memory has 1023 locations and can be pro-

grammed through addresses 0x31000 - 0x313FE. The shadow calendar memory also has 1023 locations and

can be programmed through addresses 0x31400 - 0x317FE.

• After programming the calendar memory, the TX_CAL_MEM_SEL bit is set to ‘0’.

• The calendar length register TX_CAL_LEN_MAIN is set to 16 (address 30922 and 30923 in SPIA, 30A22 and

30A23 in SPIB).

Port

Bandwidth

8-Bit Port ID

(Port Address)

STS-12

0x00

STS-12

0x01

STS-12

0x02

STS-3

0x03

STS-3

0x04

STS-3

0x05

STS-3

0x06

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