ORSPI4 datasheet(93/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

Figure 38. Read Timing with ERR Asserted - 64-Bit Mode

In the 128-bit data aggregation mode, DPRAMs 0,1,2 and 3 are used as a single contiguous memory. All DPRAMs

must be conﬁgured identically by software. In 128-bit aggregation mode, a maximum of 8 per-port buffers are pos-

sible. One signiﬁcant difference between the 128-bit mode and the 32-bit and 64-bit modes is that the port ID is

presented to the user on a separate bus (SPIA_RX128_PORTID[7:0]). Thus the SPIA_RX128_CTL signal has no

relevance to the user and can be ignored. Read data is presented as a 128-bit word every clock cycle. As shown in

Figure 39, read enable SPIA_RX128_RD and address SPIA_RX128_ADDR are presented in clock cycle T1. In T3

read data is available to the user after 2 clock cycles of latency. The FIFO address is changed to ‘p’ during the sec-

ond last word of address ‘n’ such that the 2 clock cycles of latency between address and data can be absorbed.

As shown in Figure 40, when the ASTOP_ON_EOP is asserted, two idle clock cycles are inserted after an EOP

occurs. During these idle cycles, the byte enable bits are set to all ‘0s indicating that the read data is not valid. After

the idle cycles, the core continues to provide read data. The ASTOP_ON_EOP signal can be asserted anytime and

held high for any length of time during a read data transfer.

At any time, the user can poll for the status of a FIFO within a DPRAM bank by providing just the read address

SPIA_RX128_ADDR without providing the read enable. Note that the timing diagram shown in Figure 39, Figure 40

and Figure 41 indicate a FIFO size of 64 locations. Each location contains a 128-bit word. Thus when

SPIA_RX64_CLK_j

….

SPIA_RX64_RD_j

SPIA_RX64_FIFO_EMPTY_j

SPIA_RX64_DATA_j[63:0]

2 cycles after read

enable

SPIA_RX64_CTL_j

SPIA_RX64_SOP_j

SPIA_RX64_EOP_j

na = word 0 from pointer location in

FIFO address n

nb = word 1

FIFO size = 32 locations.

SPIA_RX64_ADDR_j

ASTOP_ON_EOPj

SPIA_RX64_BE_j[7:0]

j = 0,1

SPIA_RX64_ERR_j

hff

h01

Port ID

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