ORSPI4 datasheet(43/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

Figure 14. 64-Bit Write Protocol Using Fast Back-to-Back Transfers

As with Figure 13, the FPGA initiates the start of a packet by asserting the FIFO partition address, WE, Data and

other pertinent control signals in Figure 14. During clock cycle 2, an entire 128-bit line has been written and the

internal logic increments it’s write pointer to the next location within the FIFO partition. During clock cycle 3, the

FPGA begins writing to a different DPRAM FIFO using a back-to-back transfer. A new Partition address and Port ID

are presented to the DPRAM. Since this is the Start of the Packet, the SOP is asserted. During clock cycle 5, the

internal write pointer is advanced to the next address within the FIFO partition range. On clock cycle 6, the FPGA

terminates the packet by asserting the EOP signal. The internal DPRAM Write Pointer advances during clock cycle

6 to the next location and then waits for the FPGA to attempt another write access to a partition within the DPRAM.

Beginning with clock cycle 7, the FPGA resumes writing to the original port. The FPGA presents the correct Parti-

tion address and asserts the required control signals. The internal write pointer decodes the Partition address and

sets the internal write pointer to address 'n+1'. As with 32-bit mode, in 64-bit aggregation mode, data may be writ-

ten to different Ports in a fast back-to-back fashion without any reduction in data throughput. During clock cycle 8,

the FPGA terminates writing to the current packet by asserting the EOP input signals and the correct number of BE

signals.

Figure 15 below shows the protocol required when operating in 128-bit aggregation mode. A single write from the

FPGA ﬁlls an entire line within a FIFO partition.

SPI_TX64_CLK

SPI_TX64_WD_CNT_RST

SPI_TX64_ADDR[2:0]

SPI_TX64_WE

SPI_TX64_DATA[63:0]

SPI_TX64_SOP

SPI_TX64_EOP

SPI_TX64_PORT[7:0]

SPI_TX64_BE[7:0]

Internal DPRAM Write Ptr.

Addr 'n'

Addr 'm'

'm+1'

'n+1'

Note: SPIB is identical to SPIA

Part. Addr 'k'

Partition Addr 'k+4'

0xFF

0xFC

0xFF

0xC0

Port 7

Port 3

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