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ORCA ORSPI4 Data Sheet

Status

I/Os

SPIA_RX64_PORT_ID[7:0]

FPGA

→ Core Port ID used by the core as write address into the status RAM.

SPIA_RX64_STAT[1:0]

FPGA

→ Core Port Status corresponding to SPIA_RX64_PORT_ID

SPIA_RX64_EXT_STAT_EN

FPGA

→ Core When set to ‘1’, the status from SPIA_RX64_STAT will be sent on the SPI4

status i/f.

SPIA_RX64_PSS_WE

FPGA

→ Core Write enable to the internal Status RAM.

SPIA_RX64_PSS_CLK

FPGA

→ Core Write clock to the internal Status RAM.

Misc.

I/Os

SPI_DATM_A

FPGA

→ Core Valid only during static data capture. Should be set to ‘0’ in dynamic align-

ment mode.

‘0’ - Bypass delay line circuit on the clock (ARDCLK) path.

‘1’ - Enables delay line circuit on the ARDCLK path.

SPI_DLYTAP_A[2:0]

FPGA

→ Core These bits control the effective delay of the delay line circuit on the ARD-

CLK path. Valid values are from 0-6.

ARLSCLK_F

Core

→FPGA Internal clock (ARDCLK/4) used to clock all receive status logic.

Table 13. SPIA Core Receive FPGA Interface in 64-Bit Mode (Continued)

DPRAM

FPGA Interface I/Os

Direction

From/To

Description

Note: For SPIB replace A with B

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