ORSPI4 datasheet(81/263 Pages) LATTICE

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ORCA ORSPI4 Data Sheet

Partition Address (PA): This is the least signiﬁcant 3-bit ﬁeld [2:0] within a PDM location. This ﬁeld provides the

virtual FIFO partition address for each port. Each partition is of equal size. There can be a total of 8 virtual FIFO

partitions within each DPRAM bank.

BANK_ID: This occupies bits 4:3 within a PDM location. This 2-bit ﬁeld is used to select one of the four DPRAM

banks to store the received data. The user initially assigns this information by programming the BANK_ID. Legal

values for the BANK_ID depend on the operating mode. In 32-bit mode, the legal values are 0,1,2 and 3. In 64-bit

mode, the legal values are 0 and 2. In 64-bit mode, the legal value is only 0.

While programming the PDM allocates a buffer for every port (or multiple ports), the buffer sizes themselves are

conﬁgured by the user through software register settings for

• DPRAM aggregation mode (Address 30907 for SPIA and 30A07 for SPIB. Refer to Table 18)

• Number of virtual FIFOs in a DPRAM (Address 30906 for SPIA and 30A06 for SPIB. Refer to Table 17).

Figure 31 shows a block diagram of the Port Description Memory.

Figure 31. Receive Address Mapper Block Diagram

Virtual Receive Memory FIFOs (Partitions) and Port Mapping

As was the case for the transmit logic, there are up to 32 virtual receive FIFO partitioning, 256 port numbers and

the receive calendar can contain up to 1023 entries. The user must set up the mapping between the FIFO parti-

tions and the port number for each active port. The user must also set up the calendar sequence for polling the

active ports.

The simplest mapping of the read DPRAM partitions, which support a maximum of 32 ports, is to have a 1:1 map-

ping between the FIFO partition and the port address. The 1023 depth of the calendar allows for uneven bandwidth

allocation across ports where high bandwidth ports can have multiple entries within the calendar table.

The read scheduling logic, however, is designed to support up to 256 ports. Each port (up to 32 ports) can have its

unique buffer. A single port or multiple ports can be assigned to a buffer by conﬁguring the PDM. The user must,

using FPGA logic, assure that data is read from the virtual FIFO using the same port sequencing that is expected

PDM Fields

255

BANK_ID

Port Descriptor

Software Write

Memory

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