STV0118 datasheet(10/42 Pages) STMICROELECTRONICS

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(bit ”aline” = 0)

(bit ”aline” = 1)

Full Digital Line Encoding

(720 Pixels - 1440T)

”Analog” Line Encoding

(710 Pixels - 1420T)

NTSC-M

5.38

µs(even lines)

5.52

µs(odd lines)

PAL-BDGHI

5.54

µs (A-type)

5.66

µs (B-type)

PAL-N

5.54

µs (A-type)

5.66

µs (B-type)

PAL-M

5.73

µs (A-type)

5.87

µs (B-type)

These are typical values.

Actual values will depend on the static offset programmed for subcarrier generation.

1.56

µs

8.8

µs

9.3

µs

9 Cycles of 3.58MHz

1.28

µs

9.3

µs

10.1

µs

10 Cycles of 4.43MHz

1.28

µs

9.3

µs

10.1

µs

9 Cycles of 3.58MHz

1.28

µs

9.3

µs

10.1

µs

9 Cycles of 3.58MHz

Figure 8 : Horizontal Blanking Interval and Active Video Timings

IV - FUNCTIONAL DESCRIPTION (continued)

IV.3 - Reset Procedure

Ahardware reset is performed by grounding the pin

NRESET. The master clock must be running and

pin NRESET kept low for a minimum of 5 clock

cycles. This sets the STV0118 in HSYNC+ODDEV

(line-locked) slave mode, for NTSC-M, interlaced

ITU-R601 encoding. Closed-captioning and

Teletext encoding are all disabled.

Then the configuration can be customized by wri-

ting into the appropriate registers. A few registers

are never reset, their contents is unknown until the

first loading (refer to the Register Contents and

Description).

It is also possible to perform a software reset by

setting bit’softreset’ in Reg 6. The IC’s response in

that case is similar to its response after a hardware

reset, except that Configuration Registers

(Reg 0 to 6) and a few other registers (see descrip-

tion of bit ‘softreset’) are not altered .

STV0118

10/42

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