STV0118 datasheet(14/42 Pages) STMICROELECTRONICS

14 / 42 page

HSYNC

(out)

ODDEVEN

(out)

CKREF

YCRCB

46T

CKREF

HSYNC Duration : 128T

CKREF

EAV

CKREF

Figure 14 : Data (EAV) Based Slave Mode Sync Signals

IV - FUNCTIONAL DESCRIPTION (continued)

IV.5.2.2 - VSYNC only Based Synchronization

Synchronization is performed on a frame-by-frame

basis by locking onto an incoming VSYNC signal.

An auxiliary line sync signal HSYNC must also be

fedto theSTV0118,whichuses it to reconstructfrom

VSYNC and HSYNC info rmation an internal

odd/even waveform identical to that of an ODD-

EVEN signal. Therefore the behavior of the core is

identicalto that describedabove for ODDEVEN only

basedsynchronization(exceptthat nothingis output

on HSYNC pin since it is an input port in that mode).

Note that HSYNC is an input but has no other use

than allowing the STV0118 to decide whether an

incoming VSYNC pulse flags an odd or an even

field. In other words, the STV0118 does not lock

onto HSYNC in this mode since this is NOT a

line-locked mode.

The phase relationship between VSYNC and the

incoming YCrCb data is normally such that the first

clock rising edge following the VSYNC active edge

samples “Cb” (i.e. a ‘blue’ chroma sample within

the YCrCb stream). It is however possible to inter-

na l l y del ay t h e inc omi ng s y n c s i g na l s

(VSYNC+HSYNC) by up to 3 clock cycles to cope

with different data/sync phasings, using configura-

tion bits “Syncin_ad” (Reg. 4).

IV.5.3 - Synchronization onto Data-embedded

Sync Words

IV.5.3.1 - ‘End-of-frame’ Word Based

Synchronization

Synchronization is performed by extracting the 1-

to-0 transitions of the ‘F’ flag (end-of-frame) from

the ‘EAV’ (End-of-Active Video) sequence embed-

ded within ITU-R656 / D1 compliant digital video

streams. Both a frame sync signal and a line sync

signal are derived and are made available exter-

nally as ODDEVEN and HSYNC (see Figure 14).

The first successful detection of the ‘F’ flag triggers

generationof theanalog sync signals and encoding

of the incoming video data. Frames being sup-

posed to be of constant duration, the next EAV

word containing the ‘F’ flag is expected at a precise

time after the latest detection.

So, once an active ‘F’ flag has been detected,

checks that the following flags are present within

the incoming video stream at the expected times

are performed.

Encoding and analog sync generation carry on un-

less three successive fails of these checks occur.

In that case, three behaviors are possible, accor-

ding to the configuration programmed :

- if ‘free-run’ is enabled, the STV0118 carries on

generating the digital frame and line syncs (ODD-

EVEN and HSYNC) and generating analog video

just as though the expected ‘F’ flag had been

present. However, it will re-synchronize onto the

next ‘F’ flag detected within the incoming

CCIR656/D1 video stream.

- if ‘free-run’ is disabled but the bit ‘sync_ok’ is set in

the configuration registers, the STV0118 sets the

active portion of the TV line to black level but carries

on outputtingthe analogsynctips (on Ys andCVBS)

andthedigitalframeandlinesyncsignalsODDEVEN

and HSYNC.

- if ‘free-run’is disabledandthe bit ‘sync_ok’is notset,

all analog video is at black level and neither analog

sync tips nor digital frame/line sync are output.

The SAV and EAV words are Hamming-decoded.

After detection of two successive errors, a bit is set

in the status register to inform the micro-controller

of the poor transmission quality.

IV.5.3.2 - ‘End-of-line’ Word Based

Synchronization

Synchronization is performed by extracting the ‘F’

and ‘H’ flags from the ‘SAV’ (Start of Active Video)

and ‘EAV’ (End of Active Video) words embedded

within ITU-R656/D1 compliant digitalvideo streams.

Aline sync signaland a framesync signal are derived

internally from these flags and are output on the

HSYNC and ODDEVEN/VSYNC pins in output

mode. These signals are also exploited by the core

of the circuit which treats them like it treats incoming

ODDEVEN andHSYNC signals in HSYNC+ODDEV

based synchronization (see Section IV.5.1.1).

STV0118

14/42

STV0118 数据表(PDF) 14 Page - STMicroelectronics

STV0118 数据表(HTML) 14 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

数据表下载

链接网址

STV0118 数据表(PDF) 14 Page - STMicroelectronics

STV0118 数据表(HTML) 14 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

数据表 下载

链接网址

数据表下载