VI.2 - Register Contents and Description (continued)

(*) = DEFAULT mode when NRESET pin is active (LOW level)

VI - REGISTERS (continued)

REGISTER_2 - Configuration2

MSB

LSB

Content

nintrl

enrst

bursten

xxxx

selrst

rstosc

valrst1

valrst0

Default

00

100

0

0

0

Refer to Functional Description, Section IV.7.

nintrl

Non-interlaced mode select (Refer to Figures 3, 5 and 7)

(*)

0

1

Interlaced mode (625/50 or 525/60 system)

Non-interlaced mode(2x312/50 or 2x262/60 system)

Note :

‘nintrl’ update is internally taken into account on beginning of next frame.

enrst

Cyclic update of DDFS phase

(*)

0

1

No cyclic subcarrier phase reset

Cyclic subcarrier phase reset depending of valrst1 and valrst0 (see below)

bursten

Chrominance burst control

(*)

0

1

Burst is turned off on CVBS (and CVBS1), C and RGB outputs are not affected

Burst is enabled

selrst

Selects set of reset values for Direct Digital Frequency Synthesizer

(*)

0

1

Hardware reset values for phase and increment of subcarrier oscillator

(see description of registers 10 to 14 for values)

I

rstosc

Software phase reset of DDFS (Direct Digital Frequency Synthesizer)

(*)

0

1

inactive

a 0-to-1 transition resets the phase of the subcarrier to either the hard-wired default

phase value or the value loaded in Register 13-14 (according to bit ‘selrst’)

Note :

Bit ‘rstosc’ is automatically set back to ‘0’ after the oscillator reset has been performed.

valrst[1:0] Note : valrst[1:0] is taken into account only if bit ‘enrst’ is set

valrst1 valrst0 Selection

(*)

0

0

1

1

0

1

0

1

Automatic reset of the oscillator every line

Automatic reset of the oscillator every 2nd field

Automatic reset of the oscillator every 4th field

Automatic reset of the oscillator every 8th field

Resetting the oscillator means here forcing the value of the accumulator phase to its nominal value to avoid

accumulating errors due to the finite number of bits used internally. The value to which the accumulator is

reset is either the hard-wired default phase value or the value loaded in Register 13-14 (according to bit

‘selrst’), to which a 0

°,90°, 180°, or 270° correction is applied according to the field and line on which the

reset is performed.

STV0118

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