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STV0118 数据表(PDF) 5 Page - STMicroelectronics

部件名 STV0118
功能描述  PAL/NTSC HIGH PERFORMANCE DIGITAL ENCODER
PDF  42 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STV0118 数据表(HTML) 5 Page - STMicroelectronics

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II - PIN INFORMATION (continued)
Pin
Name
Type
Function
24
CKREF
I
Master clock reference signal.
Its rising edge is the default reference for set-up and hold times of all inputs, and for
propagation delay of all outputs (except for SDA output).
CKREF nominal frequency is 27MHz (CCIR601) : input pad with pull down (50k
Ω Typ.)
25
RESET
I
Hardware reset, active LOW.
It has priority over software reset. NRESET imposes default states (see Register Contents).
Minimum Low level required duration is 5 CKREF periods : input pad with pull down
(50k
Ω Typ.)
26
SCL
I
I
2C bus clock line (internal 5-bit majority logic with CKREF for reference) : input pad with
pull down (50k
Ω Typ.)
27
SDA
I/O
I
2C bus serial data line.
Input : internal 5-bit majority logic with CKREF for reference
Output : open drain
28
VSYNC/
ODDEVEN
I/O
Frame sync signal :
- input in slave modes, except when sync is extracted from YCrCb data
- output in master mode and when sync is extracted from YCrCb data
- synchronous to rising edge of CKREF
- ODDEVEN default polarity :
odd (not-top) field : LOW level
even (bottom) field : HIGH level
II.2 - Pin Description (continued)
III - BLOCK DIAGRAM
V
SSA
V
DDA
1
2
3
4
5
6
7
8
9
16
17
18
19
20
26
27
28
11
12
13
14
15
22
23
CTRL + CFG
REGISTER
LUMA
PROCESSING
CLOSED
CAPTIONS
CGMS
CHROMA
PROCESSOR
TRAP
RGB ENCODING
CB-CR
Y
SYNC CONTROL
& VIDEO TIMING
GENERATOR
YCRCB7
I
RE F(CVBS)
VR_CVBS
CVBS
I
REF(RGB)
VR_RGB
B/CVBS
V
SSA
V
DDA
G/Y
R/C
TTXD
9-BIT
DAC
TELETEXT
YCRCB6
YCRCB5
YCRCB4
YCRCB3
YCRCB2
YCRCB1
YCRCB0
21
V
DD
10
V
SS
CSI2C
TTXS
STV0118
SDA
SCL
I2C BUS
CSI2C
VSYNC/ODDEVEN
HSYNC
25
RESET
24
CKREF
TTXS/
CSI2C
V
SSA
V
DDA
AUTOTEST
COLOR BAR
PATTERN
STV0118
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