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STV0118 数据表(PDF) 21 Page - STMicroelectronics

部件名 STV0118
功能描述  PAL/NTSC HIGH PERFORMANCE DIGITAL ENCODER
PDF  42 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STV0118 数据表(HTML) 21 Page - STMicroelectronics

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01
23
45
67
8
-80
-70
-60
-50
-40
-30
-20
-10
0
(x106) (Hz)
Figure 29 : Logarithmic PSD Scale
IV - FUNCTIONAL DESCRIPTION (continued)
IV.16 - I
2C Bus
An external micro-controller controls the STV0118
via an I
2C busby writing into or readingfrom internal
registers. The I
2C interface supports the “fast
I
2C protocol”(up to 400kHz- and potentially more).
The default I
2C addresses of the STV0118 are :
- in write mode : “01000000” (40 hex)
- in read mode : “01000001” (41 hex)
After a hardware reset, it is these addresses that
the STV0118 recognizes.
It is possible to modify the default I
2C address by
tiing the TTXS/CSI2C pin to logic ‘1’ and validat-
ing the change by writing into a dedicated bit in
Register 6.
In that case, the STV0118 has a new I
2C address:
- in write mode : “01000010” (42 hex)
- in read mode : “01000011”(43 hex)
Once the I
2C addresshas been changed, it cannot
be modifed anymore until the next hardware reset.
Note that these I
2C addresses are the same as
those used by the STV0117/STV0117A/STV0119
(others SGS-THOMSON PAL/NTSC Digital En-
coder).
It is expected that I
2C address changes will nor-
mally be needed for dual encoding applications.
The exact procedure to change the I
2C addresses
is detailed below, in the section that deals with dual
encoding applications.
Write and read operations are described in Fig-
ures 30 and 31.
SCL
SDA
R/W
A7
A6
A5
A4
A3
A2
A1
A0
D5
D4
D3
D2
D1
D0
I2 C Slave Address 40h
ACK by
STV0119
LSB Address
Start
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Data Byte 2
Data Byte 3
Data Byte n
Stop
SCL
SDA
Data Byte 1
D6
D7
ACK by
STV0119
ACK by
STV0119
ACK by
STV0119
ACK by
STV0119
ACK by
STV0119
Figure 30 : I
2C Write Operation (default address at power-on, CSI2C
≠ ’1’)
SCL
SDA
R/W
A7
A6
A5
A4
A3
A2
A1
A0
I2C Slave Address 40h
LSB Address
Start
SCL
SDA
R/W
D7
D6
D5
D4
D3
D2
D1
D 0
Data Byte n
Start
D 7
D6
D5
D4
D3
D2
D1
D0
Stop
Data Byte 1
I2C Slave Address 41h
Stop
ACK by
STV0119
ACK by
STV0119
ACK by
micro
ACK by
STV0119
ACK by
micro
Figure 31 : I
2C Read Operation (default address at power-on, CSI2C
≠ ’1’)
STV0118
21/42



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