VI.2 - Register Contents and Description

(*) = DEFAULT mode when NRESET pin is active (LOW level)

VI - REGISTERS (continued)

REGISTER_0 - Configuration0

MSB

LSB

Content

std1

std0

sync2

sync1

sync0

polh

polv

freerun

Default

10

010

0

1

0

std[1:0]

std1 std0 Standard Selected

(*)

0

0

1

1

0

1

0

1

PAL BDGHI

PAL N (see bit set-up)

NTSC M

PAL M

Note 1 : Standard on hardware reset is NTSC; any standard modification selects automatically the right parameters for

correct subcarrier generation.

sync[2:0] sync2 sync1 sync0 Configuration

(refer to Functional Description, Sections IV.4 and IV.5)

(*)

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

ODDEVEN based SLAVE mode (frame locked)

F only based SLAVE mode (frame locked)

ODDEV+HSYNC based SLAVE mode (line locked)

‘F’+’H’ based SLAVE mode (line locked)

VSYNC-only based SLAVE mode (frame locked) (see Note)

VSYNC+HSYNC based SLAVE mode (line locked)

MASTER mode

AUTOTEST mode (color bar pattern)

Caution :

In VSYNC-only based slave mode (sync[2:0]=”100”), HSYNC is nevertheless needed as an input.

Refer to Functional Description, Section IV.5.2.2.

polh

Synchro : active edge of HSYNC selection (when input)

or polarity of HSYNC (when output)

(*)

0

1

polv

Synchro : active edge of ODDEVEN/VSYNC selection (when input)

or polarity of ODDEV (when output) - See Note 2

(*)

0

1

Falling edge of ODDEVEN flags start of field1 (odd field) or VSYNC is active low

Rising edge of ODDEVEN flags start of field1 (odd field) or VSYNC is active high

Note 2 : In master mode : polarity of ODDEVEN output.

In slave by F (from EAV) : polv = 0 (cf D1 encoding) and ODDEVEN polarity is the image of F extracted

from EAV words.

freerun

Refer to Functional Description, Section IV.5

(*)

0

1

disabled

Enabled

Caution :

This bit is taken into account in ODDEV-only, VSYNC-only or ‘F’ based slave modes and is irrelevant to other

synchronization modes.

STV0118

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