VI.2 - Register Contents and Description (continued)

(*) = DEFAULT mode when NRESET pin is active (LOW level)

VI - REGISTERS (continued)

REGISTERS_10_11_12- Increment_dfs : Increment for digital frequency synthesizer

MSB

LSB

register_10

d23

d22

d21

d20

d19

d18

d17

d16

register_11

d15

d14

d13

d12

d11

d10

d9

d8

register_12

d7

d6

d5

d4

d3

d2

d1

d0

These registers contain the 24-bit increment used by the DDFS if bit ‘selrst’ equals ‘1’ to generate the

frequencyof the subcarrier i.e. the address that is supplied to the sineROM. It thereforeallows to customize

the subcarrier frequency synthesized. Refer to Functional Description, Section IV.7.

1 LSB ~ 1.6 Hz

The procedure to validate usage of these registers instead of the hard-wired values is the following :

- Load the registers with the required value

- Set bit ‘selrst’ to 1 (Reg 2)

- Perform a software reset (Reg 6)

Notes : The values loaded in Reg10-11-12 are taken into account after a software reset, and ONLY IF bit

‘selrst’=’1’ (Reg. 2)

These registers are never reset and must be explicitly written into to contain sensible information.

On hardware reset (=> ‘selrst’=0) or on soft reset with selrst=’0’, the DDFS is initalized with a

hardwired increment, independent of Registers 10-12. These hardwired values being out of any

user register these cannot be read out of the STV0118.

These values are :

Value

Frequency Synthesized

Ref.Clock

d[23:0] : 21F07C hexa for NTSC M (*)

f = 3.5795452MHz

27MHz

d[23:0] : 2A098B hexa for PAL BGHIN

f = 4.43361875 MHz

27MHz

d[23:0] : 21F694 hexa for PAL N

f = 3.5820558MHz

27MHz

d[23:0] : 21E6F0 hexa for PAL M

f = 3.57561149MHz

27MHz

‘NTSC-4.43’ can be obtained with d[23:0] value like for PALBGHI but with standardfixed as NTSC.

REGISTERS_13_14 - Phase_dfs : Static phase offset for digital frequency synthesizer (10 bits only)

MSB

LSB

register_13

----

--

o23

o22

register_14

o21

o20

o19

o18

o17

o16

o15

o14

Under certain circumstances (detailed below), these registers contain the 10 MSBs of the value with which

the phase accumulator of the DDFS is initialized after a 0-to-1 transition of bit ‘rstosc’ (Reg 2), or after a

standardchange, or when cyclic phase readjustment has been programmed (see bits valrst[1:0] of Reg 2).

The 14 remaining LSBs loaded into the accumulator in these cases are all ‘0’s (this allows to define the

phase reset value with a 0.35

°accuracy).

The procedure to validate usage of these registers instead of the hard-wired values is the following :

- Load the registers with the required value

- Set bit ‘selrst’ to 1 (Reg 2)

- Perform a software reset (Reg 6)

Notes : Registers 13-14 are never reset and must be explicitly written into to contain sensible information.

If bit ‘selrst’=0 (e.g. after a hardware reset) the phase offset used to reinitialize the DDFS is the

hard-wired value. The hard-wired values being out of any register, they cannot be read out of the

STV0118.

These are :

- D9C000hex for PAL BDGHI, N, M

- 1FC000hex for NTSC-M

STV0118

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