VI.2 - Register Contents and Description (continued)

(*) = DEFAULT mode when NRESET pin is active (LOW level)

VI - REGISTERS (continued)

REGISTER_15 : Reserved

REGISTER_16 : Reserved

REGISTER_17 : chipID (read only) : STV0118 Identification Number

0 11101 1 0 (codes 118 in binary format)

REGISTER_18 : revID (read only) : STV0118 Revision Number

0 00000 0 1 (for first revision)

REGISTER_19 : Reserved

REGISTER_20 : Reserved

REGISTERS_21_22_23: line_reg = ltarg[8:0] and lref[8:0]

MSB

LSB

register_21

ltarg8

ltarg7

ltarg6

ltarg5

ltarg4

ltarg3

ltarg2

ltarg1

register_22

ltarg0

lref8

lref7

lref6

lref5

lref4

lref3

lref2

register_23

lref1

lref0

-

-

----

These registers may be used to jump from a reference line (end of that line) to the beginning of a target

line of the SAME FIELD.

However, not all lines can be skipped or repeated with no problem and, if needed, this functionality has to

BE USED WITH CAUTION.

lref[8:0] contains in binary format the reference line from which a jump is required. ltarg[8:0] contains the

target line binary number.

Default values: lref[8:0] = 000000000 and ltarg[8:0] = 000000001

REGISTER_31-32-33 - cgms_bit[1:20] : CGMS Data registers (20 bits only)

MSB

LSB

register_31

----

b1

b2

b3

b4

register_32

b5

b6

b7

b8

b9

b10

b11

b12

register_33

b13

b14

b15

b16

b17

b18

b19

b20

These registers are never reset.

Word0A => bit1....bit3

Word0B => bit4....bit6

Word1 => bit7....bit10

Word2 => bit11....bit14

CRC => bit15...bit20 (not internally computed)

Refer to Functional Description, Section IV.14

STV0118

37/42