TAS3218IPZP datasheet(30/79 Pages) TI

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Start

Condition

Stop

Condition

Acknowledge

I C Device Address and

Read/ Write Bit

Sub Address

First Data Byte

Other Data Bytes

Last Data Byte

Acknowledge

R/W Ack

Ack

Stop

Condition

Acknowledge

I C Device Address

and

Read/Write Bit

I C Device Address

and

Read/Write Bit

Sub Address

First Data Byte

Other Data Bytes

Last Data Byte

Acknowledge

Not

Acknowledge

Ack

R/W Ack

Ack

R/W Ack

Start

Condition

Repeat Start

Condition

TAS3218

SLES235 – JULY 2008 ....................................................................................................................................................................................................... www.ti.com

Multiple Byte Write

A multiple byte data write transfer is identical to a single byte data write transfer except that multiple data bytes

are transmitted by the master device to slave as shown in Figure 20. After receiving each data byte, the

TAS3218 will respond with an acknowledge bit.

Figure 20. Multiple Byte Write Transfer

Multiple Byte Read

A multiple byte data read transfer is identical to a single byte data read transfer except that multiple data bytes

are transmitted by the TAS3218 to the master device as shown in Figure 21. Except for the last data byte, the

master device will respond with an acknowledge bit after receiving each data byte.

Figure 21. Multiple Byte Read Transfer

Random I2C Transactions

Supplying a subaddress for each subaddress transaction is referred to as random I2C addressing. For random

I2C read commands, the TAS3218 responds with data, a byte at a time, starting at the sub address assigned, as

long as the master device continues to respond with acknowledges. If a given sub address does not use all 32

bits, the unused bits are read as logic 0. I2C write commands, however, are treated in accordance with the data

assignment for that address space. If a write command is received for a biquad sub address, for example, the

TAS3218 expects to see five 32-bit words. If fewer than five data words have been received when a stop

command (or another start command) is received, the data received is discarded.

Sequential I2C Transactions

The TAS3218 supports sequential I2C addressing. For write transactions, if a sub address is issued followed by

data for that sub address and the fifteen sub addresses that follow, a sequential I2C write transaction has taken

place, and the data for all 16 sub addresses is successfully received by the TAS3218. For I2C sequential write

transactions, the sub address then serves as the start address and the amount of data subsequently transmitted,

before a stop or start is transmitted, determines how many sub addresses are written to. As was true for random

addressing, sequential addressing requires that a complete set of data be transmitted. If only a partial set of data

is written to the last sub address, the data for the last sub address is discarded. However, all other data written is

accepted; just the incomplete data is discarded.

Sequential read transactions do not have restrictions on outputting only complete sub address data sets.

If the master does not issue enough data received acknowledges to receive all the data for a given sub address,

the master device simply does not receive all the data.

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