TAS3218IPZP datasheet(10/79 Pages) TI

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Digital Audio Data Formats

LRCLK (note reversed phase)

SCLK

2-Channel I S (Philips Format) Stereo Input

Left Channel

Right Channel

LSB

MSB

LSB

32 clks

24-Bit Mode

20-Bit Mode

16-Bit Mode

23 22 21 20 19 18 17 16 15 14 13

12 11

23 22 21 20 19 18 17 16 15 14 13

12 11

19 18 17 16 15 14 13

12 11

15 14 13

12 11

19 18 17 16 15 14 13

12 11

15 14 13

12 11

TAS3218

SLES235 – JULY 2008 ....................................................................................................................................................................................................... www.ti.com

MCLKOUT, SCLKOUT, and LRCLKOUT are passed through from the clock inputs MCLKIN, SCLKIN, and

LCLKIN.

• MCLKIN 256 Fs is supplied externally

• SCLKIN 64 Fs is supplied externally

• LRCLKIN Fs is supplied externally

NOTE:

In slave mode all incoming serial audio data must be synchronous to an incoming

LRCLKIN of 32, 44.1 or 48 kHz. The TAS3218 does not support the use of an

external (i.e., 24 MHz) clock input through into XTALI

Serial data is input on pins SDIN1-3 on the TAS3218, allowing up to 6 channels of digital audio input. The

TAS3218 supports 16-, 20-, or 24-bit data in left, right, or I2S serial data format. By default, all TAS3218 serial

digital inputs are configured in the 24-bit I2S format. The serial data input format is configurable via the

SAP/Clock Settings Register.

Serial data is output on pins SDOUT1-2, allowing up to 4 channels of digital audio output. By default, the SDOUT

data format is 24-bit, I2S format at the same data rate as the input. The SDOUT1-2 output uses the SCLKOUT

and LRCLKOUT signals to provide synchronization. SDOUT2 is multiplexed with an SPDIF output.

NOTE:

To avoid audio artifacts, I2C commands to reconfigure the serial audio port (SAP)

should not be issued as standalone commands, rather should be accompanied by

mute and unmute commands.

The TAS3218 uses the SCLK as a reference for both input and output samples. The negative edge of SCLK is

used to output a new data bit, where as the positive edge of SCLK is used to sample incoming serial data.

Discrete I2S Timing

I2S timing uses an LRCLK to define when the data being transmitted is for the left channel and when it is for the

right channel. The LRCLK is LOW for the left channel and HIGH for the right channel. A bit clock running at 64

Fs is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes state to

the first bit of data on the data lines. The data is written MSB first and is valid on the rising edge of bit clock. The

TAS3218 will mask unused trailing data bit positions.

All data are presented in 2's complement form with MSB first.

Figure 5. SAP I2S Format 64 Fs Format

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