TAS3218IPZP datasheet(54/79 Pages) TI

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Slave I

2C Load RAM Block Formats

TAS3218

SLES235 – JULY 2008 ....................................................................................................................................................................................................... www.ti.com

Table 13. DSP Data RAM Block Structure

STARTING

DATA BLOCK FORMAT

SIZE

VALUE

NOTES

BYTE

Checksum MSB

2 byte

Checksum of byte 2 through N + 12

Checksum LSB

Header ID byte 1

0x00

2 byte

Must be 0x001F

Header ID byte 2

0x1F

Micro program RAM or micro external

Memory to be loaded

1 byte

0x04

data RAM

0x00

1 byte

0x00

Unused

Start memory address

MSB

If this is a termination header, this

2 byte

value is 0000

Start memory address

LSB

Total number of byte

transferred MSB

2 byte

Header (12) + data (N) + checksum (4)

Total number of byte

transferred LSB

0x00

1 byte

0x00

Unused

0x00

1 byte

0x00

Unused

Data byte 1 (LSB)

Data word 1 D7D0

Data byte 2

D15D8

Data byte 3

D23D16

6 byte

Data byte 4 (MSB)

D31D24

Data byte 5

D39D32

Data byte 6 (MSB)

D47D40

Data byte 7 (LSB)

Data byte 8

Data byte 9

6 byte

Data word 2

Data byte 10

Data byte 11

Data byte 12 (MSB)

0x00

Repeated checksum byte 2 through N

N + 12

6 byte

+11

Checksum MSB

Checksum LSB

The slave I2C bus permits the system controller to load the TAS3218 memories as an alternative to using the

master download from an external memory device via the I2C master bus. The transfer is performed by writing to

two I2C registers (0x04 and 0x05). The first register holds the header information, and the second register holds

eight bytes of data. Figure 39 shows the I2C slave download flow.

I2C slave download register format are described in Table 14 to Table 18. The I2C slave download process is

terminated when a termination header with zero length byte count field is received.

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