TAS3218IPZP datasheet(34/79 Pages) TI

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Digital Signal Processor (DSP) Arithmetic Unit

Overview

TAS3218

SLES235 – JULY 2008 ....................................................................................................................................................................................................... www.ti.com

The arithmetic processor is a fixed-point computational engine consisting of an arithmetic unit and data and

coefficient memory blocks. The primary features are:

• Two pipe parallel processing architecture

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48-bit datapath with 76-bit accumulator

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Hardware single cycle multiplier (28 48)

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Three 48-bit general purpose data registers

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One 28 bit coefficient register

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48-bit adder

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28-bit adder

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Shift right, shift left

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Bi-modal clip

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Log2/Alog2

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Magnitude truncation

• Read/read/write single-cycle memory access

• Data input is 48-bit 2s complement multiplexed in from SAP immediately following FSYNC pulse

• Data output is four 32-bit 2s complement busses

• Separate control for writing to delay memory

• Separate coefficient memory (28-bit) and data memory (48-bit)

• Linear Feedback Shift Register (LFSR) in the instruction register doubles as a random number generator in

normal operating mode

• Coefficient RAM, Data RAM, LFSR seed, Program counter, and memory pointers are all mapped into the

same memory space for convenient addressing by the micro

• Memory interface block contains four pointers, two for data memory and two for coefficient memory

Data Format

Figure 24 shows the data word structure of the arithmetic unit. Eight bits of overhead or guard bits are provided

at the upper end of the 48-bit word, and 16 bits of computational precision or noise bits are provided at the lower

end of the 48-bit word. The incoming digital audio words are all positioned with the most significant bit abutting

the 8-bit overhead/guard boundary. The sign bit in bit 39 indicates that all incoming audio samples are treated as

signed data samples.

The arithmetic engine is a 48-bit (25.23 format) processor consisting of a general-purpose 76-bit arithmetic logic

unit and function-specific arithmetic blocks. Multiply operations (excluding the function-specific arithmetic blocks)

always involve 48-bit words and 28-bit coefficients (usually I2C programmable coefficients). If a group of products

are to be added together, the 76-bit product of each multiplication is applied to a 76-bit adder, where a DSP-like

multiply-accumulate (MAC) operation takes place. Biquad filter computations use the MAC operation to maintain

precision in the intermediate computational stages.

To maximize the linear range of the 76-bit ALU, saturation logic is not used. In MAC computations, intermediate

overflows are permitted, and it is assumed that subsequent terms in the computation flow will correct the

overflow condition.

The memory banks include a dual port data RAM for storing intermediate results, a coefficient RAM, and a fixed

program ROM. Only the coefficient RAM, assessable via the I2C bus, is available to the user.

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