TAS3218IPZP datasheet(29/79 Pages) TI

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2C Control Interface

General I2C Transactions

Start

(by master)

Acknowledge

(by TAS3208)

(See Note A)

Start Condition

I2C_SDA

while I2C_SCL = 1

↓

MSB

MSB–1

MSB–2

LSB

Stop Condition

I2C_SDA

while I2C_SCL = 1

↑

Acknowledge

(by receiver)

Acknowledge

(by receiver)

Read or Write

(by master)

Stop

(by master)

I2C_SDA

I2C_SCL

Data Byte

(by transmitter)

Slave Address

(By master)

Data Byte

(by transmitter)

TAS3218

www.ti.com ....................................................................................................................................................................................................... SLES235 – JULY 2008

The M8051 microprocessor receives and distributes I2C data to the I2C bus controllers, and participates in most

I2C processing tasks requiring multi-frame processing cycles. The master and slave interfaces do not operate

simultaneously.

The I2C communication protocol for the I2C slave mode is shown in Figure 19.

Bits CS1 and CS0 in the TAS3218 slave address are compared to the logic levels on pins CS0 and CS1 for address

verification. This provides the ability to address up to four TAS3218 chips on the same I2C bus.

Figure 19. I2C Slave Mode Communication Protocol

The I2C bus employs two signals; SDA (data) and SCL (clock), to communicate between integrated circuits in a

system. Data is transferred on the bus serially one bit at a time. The address and data be transferred in byte

(8-bit) format with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is

acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master

device driving a start condition on the bus and ends with the master device driving a stop condition on the bus.

The bus uses transitions on the data terminal (SDA) while the clock is HIGH to indicate a start and stop

conditions. A HIGH-to-LOW transition on SDA indicates a start, and a LOW-to-HIGH transition indicates a stop.

Normal data bit transitions must occur within the low time of the clock period. The master generate the 7-bit slave

address and the read/write (R/W) bit to open communication with another device and then wait for an

acknowledge condition. The slave holds SDA LOW during acknowledge clock period to indicate an

acknowledgement. When this occurs, the master transmits the next byte of the sequence. Each device is

addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same signals

via a bi-directional bus using a wired-AND connection. An external pull-up resistor must be used for the SDA and

SCL signals to set the HIGH level for the bus.

There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last

word transfers, the master generates a stop condition to release the bus.

A read transaction requires that the master device first issue a write transaction to give the TAS3218 the sub

address to be used in the read transaction that follows. This sub address assignment write transaction is then

followed by the read transaction. For write transactions, the sub address is supplied in the first byte of data

written, and this byte is followed by the data to be written. For write transactions, the sub address must always

be included in the data written. There cannot be a separate write transaction to supply the sub address, as was

required for read transactions. If a subaddress assignment only write transaction is followed by a second write

transaction supplying the data, erroneous behavior results. The first byte in the second write transaction is

interpreted by the TAS3218 as another sub address replacing the one previously written.

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