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TAS3218IPZP 数据表(PDF) 45 Page - Texas Instruments |
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TAS3218IPZP 数据表(HTML) 45 Page - Texas Instruments |
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45 / 79 page  ELECTRICAL CHARACTERISTICS MASTER CLOCK SIGNALS TAS3218 www.ti.com ....................................................................................................................................................................................................... SLES235 – JULY 2008 over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 3.3-V TTL IOH = 4 mA 2.4 VOH High-level output voltage, V 1.8-V LVCMOS (XTL_OUT) IOH = 0.55 mA 1.44 3.3-V TTL IOL = 4 mA 0.5 VOL Low-level output voltage V 1.8-V LVCMOS (XTL_OUT) IOL = 0.75 mA 0.396 High-impedance output IOZ 3.3-V TTL 20 A current, 1.8-V LVCMOS (XTL_IN) 1 IIL Low-level input current(1) VI = VIL A 3.3-V TTL 1 1.8-V LVCMOS (XTL_IN) 1 IIH High-level input current(2) VI = VIH A 3.3-V TTL 1 DSP clock = 135 MHz, LRCLKIN/LRCLKOUT = 48 IDVDD Digital supply current 200 mA KHz, XTALI = 24.288 MHz DSP clock = 135 MHz, LRCLKIN/LRCLKOUT = 48 IAVDD Analog supply current 28 mA KHz, XTALI = 24.288 MHz IDVDD Digital supply current RESET = LOW 0.1 mA IAVDD Analog supply current RESET = LOW 5 mA (1) Value given is for those input pins that connect to an internal pullup resistor as well as an input buffer. For inputs that have a pulldown resistor or no resistor, IIL is 1 A. (2) Value given is for those input pins that connect to an internal pulldown resistor as well as an input buffer. For inputs that have a pullup resistor or no resistor, IIH is 1 A. over recommended operating conditions, see Figure 33 PARAMETER MIN TYP MAX UNIT 24.576 fXTALI XTALI frequency (1/ tcyc1) (1) MHz (512 Fs) tcyc1 XTALI cycle time(2) 1/(512 Fs) ns fMCLKIN MCLKIN frequency (1/ tcyc2) 256 Fs MHz twMCLKIN MCLKIN pulse duration(3) 0.4 tcyc2 0.6 tcyc2 ns fMCLKOUT MCLKOUT frequency(1/ tcyc3) 256 Fs MHz trMCLKOUT MCLKOUT rise time CL = 30 pF 10 ns tfMCLKOUT MCLKOUT fall time CL = 30 pF 10 ns twMCLKOUT MCLKOUT pulse duration(4) 0.4 tcyc3 0.6 tcyc3 ns XTALI master clock MCLKOUT jitter 80 ps source Delay time, tdMIMO MCLKIN rising edge to MCLKOUT rising MCLKOUT = MCLKIN 17 ns edge (5) (1) Frequency tolerance is 100 ppm (or better) at 25C. (2) tcyc1 = 1/ fXTALI (3) tcyc2 = 1/ fMCLKIN (4) tcyc3 = 1/ fMCLKOUT (5) When MCLKOUT is derived from MCLKIN, MCLKOUT jitter = MCLKIN jitter. MCLKOUT has the same duty cycle as MCLKIN when MCLKOUT = MCLKIN. Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 45 Product Folder Link(s): TAS3218 |
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