TAS3218IPZP datasheet(64/79 Pages) TI

64 / 79 page

Load Memory Control and Data Register (0x04 and 0x05)

TAS3218

SLES235 – JULY 2008 ....................................................................................................................................................................................................... www.ti.com

Bits 4032 define the memory load error status on EEPROM download and slave download.

Table 26. Analog Busy(1)

ANALOG BUSY FLAG

ABSY

Analog is busy

Analog not busy

(1)

Default values are shown in italics.

Analog control sequence takes time (maximum around 500 ms for headphone power up). This busy flag indicate

whether analog control sequence is running or not.

Table 27. I2C Bus Error(1)

I2C BUS ERROR

BUSE

Bus error

No bus error

(1)

Default values are shown in italics.

If I2C bus error occurs, this flag will be set. Only host uC can clear this flag by writing 0 to this bit. I2C bus error

status is read from ESFR (0xC5, bit 6), and is cleared by ESFR (0xC7, bit 6).

The I2C Memory Load port permits the system controller to load the TAS3218 memories as an alternative to

having the TAS3218 load its memory from an external EEPROM.

The transfer is performed by writing to two I2C registers. The first register is a eight byte register than holds the

check sum, the memory to be written, the starting address, the number of data bytes to be transferred. The

second register holds eight bytes of data.

The memory load operation starts with the first register being set. Then the data is written into the second

bytes are written which constrain the two byte checksum. At that point, the transfer is complete and status of the

operation is reported in the status register.

NOTE:

Once the micro program memory has been loaded, further updates to this memory

are inhibited until the device is RESET.

When the first I2C slave down load register is written by the system controller the TAS3218 will update the status

when the operation complete and a valid checksum has been received.

For example when the Micro program memory is being loaded, the TAS3218 will set a Micro program memory

error indication in the status register at the start of the sequence. When the last byte of the micro program

memory and checksum is received, the TAS3218 will clear the micro program memory error indication. This

enables the TAS3218 to preserve any error status indications that occur as a result of incomplete transfers of

data/ checksum error during a series of data and program memory load operations.

The checksum is always contained in the last two bytes of the data block.

The I2C slave download is terminated when a termination header with a zero length byte count filed is received.

Submit Documentation Feedback

Product Folder Link(s): TAS3218

TAS3218IPZP 数据表(PDF) 64 Page - Texas Instruments

TAS3218IPZP 数据表(HTML) 64 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79

数据表下载