ADE5166 datasheet(44/148 Pages) AD

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ADE5166/ADE5169

Rev. 0 | Page 44 of 148

Antialiasing Filter

Figure 41 also shows an analog LPF (RC) on the input to the

modulator. This filter is present to prevent aliasing, an artifact

of all sampled systems. Aliasing means that frequency components

in the input signal to the ADC, which are higher than half the

sampling rate of the ADC, appear in the sampled signal at a fre-

quency below half the sampling rate. Figure 42 illustrates the effect.

Frequency components (the black arrows) above half the sampling

frequency (also known as the Nyquist frequency, that is, 409.6 kHz)

are imaged or folded back down below 409.6 kHz. This happens

with all ADCs, regardless of the architecture. In Figure 42, only

frequencies near the sampling frequency (819.2 kHz) move into

the band of interest for metering (40 Hz to 2 kHz). This allows

the use of a very simple LPF to attenuate high frequency (at

approximately 819.2 kHz) noise and prevents distortion in the

band of interest.

409.6

819.2

FREQUENCY (kHz)

SAMPLING

FREQUENCY

ALIASING EFFECTS

IMAGE

FREQUENCIES

Figure 42. ADC and Signal Processing in Current Channel Outline Dimensions

For conventional current sensors, a simple RC filter (single-pole

LPF) with a corner frequency of 10 kHz produces an attenuation

of approximately 40 dB at 819.2 kHz (see Figure 42). The 20 dB

per decade attenuation is usually sufficient to eliminate the effects

of aliasing for conventional current sensors. However, for a di/dt

sensor such as a Rogowski coil, the sensor has a 20 dB per decade

gain. This neutralizes the −20 dB per decade attenuation produced

by one simple LPF. Therefore, when using a di/dt sensor, care

should be taken to offset the 20 dB per decade gain. One simple

approach is to cascade two RC filters to produce the −40 dB per

decade attenuation needed.

ADC Transfer Function

Both ADCs in the ADE5166/ADE5169 are designed to produce

the same output code for the same input signal level. With a

full-scale signal on the input of 0.5 V and an internal reference

of 1.2 V, the ADC output code is nominally 2,147,483 or 0x20C49B.

The maximum code from the ADC is ±4,194,304; this is equiva-

lent to an input signal level of ±0.794 V. However, for specified

performance, it is recommended that the full-scale input signal

level of 0.5 V not be exceeded.

Current Channel ADC

Figure 43 shows the ADC and signal processing chain for the

current channel. In waveform sampling mode, the ADC outputs

a signed, twos complement, 24-bit data-word at a maximum of

25.6 kSPS (4.096 MHz/160).

×1, ×2, ×4,

×8, ×16

ADC

IPA

PGA1

{GAIN[2:0]}

HPF

ADC

IBP

PGA1

HPF

IBGAIN[11:0]

ADC

DFC

MULTIPLIER

INTEGRATOR

WATTOS[15:0]

VAGAIN[11:0]

VADIV[7:0]

IRMSOS[11:0]

VRMSOS[11:0]

WGAIN[11:0]

METERING SFRs

PGA2

CF1

WDIV[7:0]

VARDIV[7:0]

VAROS[15:0]

VARGAIN[11:0]

DFC

CF2NUM[15:0]

CF2DEN[15:0]

CF1DEN[15:0]

CF1NUM[15:0]

CF2

HPF

LPF

LPF2

Figure 43. ADC and Signal Processing in Current Channel with PGA1 = 2, 4, 8, or 16

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