ADE5166 datasheet(76/148 Pages) AD

76 / 148 page

ADE5166/ADE5169

Rev. 0 | Page 76 of 148

The stack resides in the upper part of the extended internal RAM.

The SP bits (Bits[7:0]) in the stack pointer SFR (SP, Address 0x81)

and the SP bits (Bits[2:0]) in the stack pointer high SFR (SPH,

Address 0xB7) hold the address of the stack in the extended

RAM. The advantage of this solution is that the use of the

general-purpose RAM can be limited to data storage. The use

of the extended internal RAM can be limited to the stack or,

alternatively, split between the stack and data storage if more

space is required. This separation limits the chance of data

corruption because the stack can be contained in the upper

section of the XRAM and does not over-flow into the lower

section containing data. Data can still be stored in extended

RAM by using the MOVX command.

The default starting address for the stack is 0x100, electing the

upper 1792 bytes of XRAM for the stack operation. The starting

address can be reconfigured to reduce the stack by writing to

the SPH[5:3] bits. These three bits set the value of the three most

significant bits of the stack pointer. For example, setting the

SPH[5:3] to a value of 110b moves the default starting address

of the stack to 0x600, allowing the highest 512 bytes of the XRAM

to be used for stack operation. If the situation occurs that the

stack reaches the top of the XRAM and overflows, the stack

pointer rolls over to the default starting address that is written

in SPH[5:3]. Care should be taken if altering the default starting

address of the stack because unwanted overwrite operations

may occur, should the stack overflow or underflow.

Stack Boundary Protection

As a warning signal that the stack pointer is extending outside

the specified range, a stack boundary protection feature is included.

This feature is controlled through the stack boundary SFR

(STCON, Address 0xBF) and is disabled by default. To enable

this feature, the boundary protection enable bit (SBE, Bit 1)

should be set in the STCON SFR.

The stack boundary protection works in two ways to protect the

remainder of the XRAM from being corrupted. The waterline

detection feature monitors the top of the stack and warns the

user when the stack pointer is reaching the overflow point. By

setting STCON[7:3], the level of the waterline below the top of

the XRAM can be set. For example, by setting STCON[7:3] to

the maximum value of 0x1F, the waterline is set to its minimum

value of 0x7FF − 0x1F = 0x7F0. Similarly, by setting STCON[7:3]

to 0x1, the waterline is set at the top of the RAM space,

Address 0x7FE. Note that if STCON[7:3] is set to 000b, the

feature is effectively disabled and no interrupt or reset is generated.

The bottom of the stack is also preserved by the stack boundary

feature. Should the stack pointer be written to a value lower

than the default stack starting address defined in SPH[5:3],

a warning is issued and the perpetrating command is ignored.

The protection for both the waterline and the stack starting

address are enabled simultaneously by setting SBE (Bit 1) in the

STCON SFR.

When enabled, the stack boundary protection can be configured

to either reset the part or trigger an interrupt when a stack viola-

tion occurs. The value of the INT_RST bit (Bit 2) of the STCON

SFR (Address 0xBF) determines the response of the part. When

STCON[2] is set to 0x1 and the stack pointer exceeds the waterline,

the part resets immediately, no matter what other routines are

in progress. If an attempt is made to move the stack pointer below

the default stack starting address when STCON[2] is high, a reset

also occurs. If an interrupt response is selected, the watchdog

interrupt service routine is entered, assuming that there is no

higher level interrupt currently being serviced. Note that once the

SBE bit (Bit 1) of the STCON SFR is enabled, an interrupt(or reset)

triggers if the stack boundary is violated, regardless of the status

of the EA bit (Bit 7) in the interrupt enable SFR (IE, Address 0xA8).

This is because the watchdog interrupt is automatically configured

as a high priority interrupt and, therefore, is not disabled by

clearing EA. When the SBE bit (Bit 1) of the STCON SFR

(Address 0xBF) is low, the feature is completely disabled and no

pending interrupts are generated.

There are two separate flags associated with the stack boundary

protection, allowing the cause of the violation to be determined.

When the waterline is exceeded, a flag is set in WTRLFG (Bit 0)

of the stack boundary SFR (STCON, Address 0xBF), indicating that

the reset/interrupt was initiated by the stack waterline monitor.

This flag remains high until the stack pointer falls below the water-

line and the user clears the flag in software. A waterline or

watchdog reset alone does not clear the flag. To successfully clear

the flag, the software clear must occur while the stack pointer is

below the waterline.

Note that the stack pointer should never be altered while in the

interrupt service routine because this leads to the program

returning to a different section of the program and, therefore,

malfunctioning. An external reset also causes the waterline flag

to reset.

When an attempt is made to move the stack pointer below the

stack starting address, a flag (SBFLG, Bit 0) is set in the stack

pointer high SFR (SPH, Address 0xB7), indicating that the reset/

interrupt was initiated by the stack bottom monitor. Once again,

a boundary or watchdog reset alone does not clear this flag, and

the user must clear the flag in software to successfully acknowledge

the event. Note that if SPH[5:3] and SPH[2:0] are altered simul-

taneously to reduce the default stack starting address, when the

stack boundary condition is enabled, a stack violation condition

occurs and the stack bottom flag, SPH[6], is initiated. To avoid

this condition, it is recommended that the default stack starting

address remain at 0x100 or be increased to further up the XRAM.

ADE5166 数据表(PDF) 76 Page - Analog Devices

ADE5166 数据表(HTML) 76 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载