ADE5166 datasheet(32/148 Pages) AD

32 / 148 page

ADE5166/ADE5169

Rev. 0 | Page 32 of 148

OPERATING MODES

PSM0 (NORMAL MODE)

In PSM0, or normal operating mode, VSWOUT is connected to VDD.

All of the analog circuitry and digital circuitry powered by

VINTD and VINTA are enabled by default. In normal mode, the

default clock frequency, fCORE, which is established during a

power-on reset or software reset, is 1.024 MHz.

PSM1 (BATTERY MODE)

In PSM1, or battery mode, VSWOUT is connected to VBAT. In this

operating mode, the 8052 core and all of the digital circuitry are

enabled by default. The analog circuitry for the ADE energy

metering DSP powered by VINTA is disabled. This analog circuitry

automatically restarts, and the switch to the VDD power supply

occurs when the VDD supply is >2.75 V and the PWRDN bit in

the MODE1 register (Address 0x0B) is cleared (see Table 32). The

default fCORE for PSM1, established during a power-on reset or

software reset, is 1.024 MHz.

PSM2 (SLEEP MODE)

PSM2 is a low power consumption sleep mode for use in battery

operation. In this mode, VSWOUT is connected to VBAT. All of the

2.5 V digital and analog circuitry powered through VINTA and VINTD

isdisabled, including the MCU core, resulting in the following:

•

The RAM in the MCU is no longer valid.

•

The program counter for the 8052, also held in volatile

memory, becomes invalid when the 2.5 V supply is shut

down. Therefore, the program does not resume from where

it left off but always starts from the power-on reset vector

when the ADE5166/ADE5169 exit PSM2.

The 3.3 V peripherals (temperature ADC, VDCIN ADC, RTC,

and LCD) are active in PSM2. They can be enabled or disabled

to reduce power consumption and are configured for PSM2

operation when the MCU core is active (see Table 28 for more

information about the individual peripherals and their PSM2

configuration). The ADE5166/ADE5169 remain in PSM2 until

an event occurs to wake them up.

In PSM2, the ADE5166/ADE5169 provide four scratch pad

RAM SFRs that are maintained during this mode. These SFRs

can be used to save data from PSM0 or PSM1 mode when

entering PSM2 mode (see Table 21 to Table 24).

In PSM2 mode, the ADE5166/ADE5169 maintain some SFRs

(see Table 27). The SFRs that are not listed in this table should

be restored when the part enters PSM0 or PSM1 mode from

PSM2 mode.

Table 27. SFRs Maintained in PSM2

I/O Configuration

Power Supply Management

RTC Peripherals

LCD Peripherals

Interrupt pins configuration SFR

(INTPR, Address 0xFF); see

Table 16.

Battery detection threshold SFR

(BATVTH, Address 0xFA); see

Table 52.

RTC nominal compensation SFR

(RTCCOMP, Address 0xF6); see Table 131.

LCD Segment Enable 2 SFR

(LCDSEGE2, Address 0xED); see

Table 100.

Peripheral configuration SFR

(PERIPH, Address 0xF4); see

Table 19.

Battery switchover configuration

SFR (BATPR, Address 0xF5); see

Table 18.

RTC temperature compensation SFR

(TEMPCAL, Address 0xF7); see Table 132.

LCD Configuration Y SFR

(LCDCONY, Address 0xB1); see

Table 93.

Port 0 weak pull-up enable SFR

(PINMAP0, Address 0xB2); see

Table 162.

Battery ADC value SFR (BATADC,

Address 0xDF); see Table 54.

RTC configuration SFR (TIMECON, Address

0xA1); see Table 127.

LCD Configuration X SFR

(LCDCONX, Address 0x9C); see

Table 91.

Port 1 weak pull-up enable SFR

(PINMAP1, Address 0xB3); see

Table 163.

Peripheral ADC strobe period SFR

(STRBPER, Address 0xF9); see

Table 49.

RTC Configuration 2 SFR (TIMECON2,

Address 0xA2); see Table 128.

LCD configuration SFR

(LCDCON, Address 0x95); see

Table 90.

Port 2 weak pull-up enable SFR

(PINMAP2, Address 0xB4); see

Table 164.

Temperature and supply delta

SFR (DIFFPROG, Address 0xF3);

see Table 50.

All indirectly accessible registers defined

in the RTC register list; see Table 134.

LCD clock SFR (LCDCLK,

Address 0x96); see Table 94.

Scratch Pad 1 SFR (SCRATCH1,

Address 0xFB); see Table 21.

VDCIN ADC value SFR (VDCINADC,

Address 0xEF); see Table 53.

LCD segment enable SFR

(LCDSEGE, Address 0x97); see

Table 97.

Scratch Pad 2 SFR (SCRATCH2,

Address 0xFC); see Table 22.

Temperature ADC value SFR

(TEMPADC, Address 0xD7); see

Table 55.

LCD Pointer SFR (LCDPTR,

Address 0xAC); see Table 98.

Scratch Pad 3 SFR (SCRATCH3,

Address 0xFD); see Table 23.

LCD data SFR (LCDDAT,

Address 0xAE); see Table 99.

Scratch Pad 4 SFR (SCRATCH4,

Address 0xFE); see Table 24

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