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ADE5166 数据表(PDF) 22 Page - Analog Devices |
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ADE5166 数据表(HTML) 22 Page - Analog Devices |
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22 / 148 page  ADE5166/ADE5169 Rev. 0 | Page 22 of 148 SPECIAL FUNCTION REGISTER (SFR) MAPPING Table 14. SFR Mapping Mnemonic Address Description INTPR 0xFF Interrupt pins configuration SFR (see Table 16). SCRATCH4 0xFE Scratch Pad 4 (see Table 24). SCRATCH3 0xFD Scratch Pad 3 (see Table 23). SCRATCH2 0xFC Scratch Pad 2 (see Table 22). SCRATCH1 0xFB Scratch Pad 1 (see Table 21). BATVTH 0xFA Battery detection threshold (see Table 52). STRBPER 0xF9 Peripheral ADC strobe period (see Table 49). IPSMF 0xF8 Power management interrupt flag (see Table 17). TEMPCAL 0xF7 RTC temperature compensation (see Table 132). RTCCOMP 0xF6 RTC nominal compensation (see Table 131). BATPR 0xF5 Battery switchover configuration (see Table 18). PERIPH 0xF4 Peripheral configuration (see Table 19). DIFFPROG 0xF3 Temperature and supply delta (see Table 50). B 0xF0 Auxiliary math (see Table 56). VDCINADC 0xEF VDCIN ADC value (see Table 53). SBAUD2 0xEE Enhanced Serial Baud Rate Control 2 (see Table 148). LCDSEGE2 0xED LCD Segment Enable 2 (see Table 100). IPSME 0xEC Power management interrupt enable (see Table 20). SBUF2 0xEB Serial Port 2 buffer (see Table 147). SPISTAT 0xEA SPI interrupt status (see Table 155). SPI2CSTAT 0xEA I2C interrupt status (see Table 159). SPIMOD2 0xE9 SPI Configuration SFR 2 (see Table 154). I2CADR 0xE9 I2C slave address (see Table 158). SPIMOD1 0xE8 SPI Configuration SFR 1 (see Table 153). I2CMOD 0xE8 I2C mode (see Table 157). WAV2H 0xE7 Selection 2 sample MSB (see Table 30). WAV2M 0xE6 Selection 2 sample middle byte (see Table 30). WAV2L 0xE5 Selection 2 sample LSB (see Table 30). WAV1H 0xE4 Selection 1 sample MSB (see Table 30). WAV1M 0xE3 Selection 1 sample middle byte (see Table 30). WAV1L 0xE2 Selection 1 sample LSB (see Table 30). SCON2 0xE1 Serial communications control (see Table 146). ACC 0xE0 Accumulator (see Table 56). BATADC 0xDF Battery ADC value (see Table 54). MIRQSTH 0xDE Interrupt Status 3 (see Table 42). MIRQSTM 0xDD Interrupt Status 2 (see Table 41). MIRQSTL 0xDC Interrupt Status 1 (see Table 40). MIRQENH 0xDB Interrupt Enable 3 (see Table 45). MIRQENM 0xDA Interrupt Enable 2 (see Table 44). Mnemonic Address Description MIRQENL 0xD9 Interrupt Enable 1 (see Table 43). ADCGO 0xD8 Start ADC measurement (see Table 51). TEMPADC 0xD7 Temperature ADC value (see Table 55). IRMSH 0xD6 Irms measurement MSB (see Table 30). IRMSM 0xD5 Irms measurement middle byte (see Table 30). IRMSL 0xD4 Irms measurement LSB (see Table 30). VRMSH 0xD3 Vrms measurement MSB (see Table 30). VRMSM 0xD2 Vrms measurement middle byte (see Table 30). VRMSL 0xD1 Vrms measurement LSB (see Table 30). PSW 0xD0 Program status word (see Table 57). TH2 0xCD Timer 2 high byte (see Table 119). TL2 0xCC Timer 2 low byte (see Table 120). RCAP2H 0xCB Timer 2 reload/capture high byte (see Table 121). RCAP2L 0xCA Timer 2 reload/capture low byte (see Table 122). T2CON 0xC8 Timer/Counter 2 control (see Table 114). EADRH 0xC7 Flash high byte address (see Table 109). EADRL 0xC6 Flash low byte address (see Table 108). POWCON 0xC5 Power control (see Table 25). KYREG 0xC1 Key (see Table 125). WDCON 0xC0 Watchdog timer (see Table 87). STCON 0xBF Stack boundary (see Table 64). EDATA 0xBC Flash data (see Table 107). PROTKY 0xBB Flash protection key (see Table 106). FLSHKY 0xBA Flash key (see Table 105). ECON 0xB9 Flash control (see Table 104). IP 0xB8 Interrupt priority (see Table 81). SPH 0xB7 Stack pointer high (see Table 63). PINMAP2 0xB4 Port 2 weak pull-up enable (see Table 164). PINMAP1 0xB3 Port 1 weak pull-up enable (see Table 163). PINMAP0 0xB2 Port 0 weak pull-up enable (see Table 162). LCDCONY 0xB1 LCD Configuration Y (see Table 93). CFG 0xAF Configuration (see Table 65). LCDDAT 0xAE LCD data (see Table 99). LCDPTR 0xAC LCD pointer (see Table 98). IEIP2 0xA9 Interrupt enable and Priority 2 (see Table 82). IE 0xA8 Interrupt enable (see Table 80). DPCON 0xA7 Data pointer control (see Table 78). RTCDAT 0xA4 RTC pointer data (see Table 130). RTCPTR 0xA3 RTC pointer address (see Table 129). TIMECON2 0xA2 RTC Configuration 2 (see Table 128). TIMECON 0xA1 RTC configuration (see Table 127). P2 0xA0 Port 2 (see Table 167). EPCFG 0x9F Extended port configuration (see Table 161). |
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