ADE5166 datasheet(77/148 Pages) AD

77 / 148 page

ADE5166/ADE5169

Rev. 0 | Page 77 of 148

A useful implementation of the waterline feature is to determine

the amount of space required for the stack and allow a suitable

default starting address to be selected. This optimizes the use

of the additional XRAM space, allowing it to be used for data

storage. To obtain this information, the waterline should be set

to the estimated stack maximum and the interrupt enabled. If

the stack exceeds the estimated maximum, the interrupt triggers,

and the waterline level should be increased in the interrupt

service routine. Before returning to the main program, the

waterline interrupt status flag (WTRLFG, Bit 0) of the stack

boundary SFR (STCON, Address 0xBF) should be cleared. This

program continues to jump to the waterline service routine

until the stack no longer exceeds the waterline level and the

maximum stack level is determined.

0xFF

0x7FF

256 BYTES

{SPH[5:3], 0x00}

0x7FF-STCON[7:3]

2kB OF

ON-CHIP x-RAM

STACK STARTING

ADDRESS

WATERLINE

OF RAM

(DATA)

0x00

Figure 77. Extended Stack Pointer Operation

STANDARD 8052 SFRS

The standard 8052 SFRs include the accumulator (ACC), B, PSW,

DPTR, and SP SFRs, as described in the Basic 8052 Registers

section. The 8052 also defines standard timers, serial port

interfaces, interrupts, I/O ports, and power-down modes.

Timer SFRs

The 8052 contains three 16-bit timers, the identical Timer 0 and

Timer 1, as well as a Timer 2. These timers can also function as

event counters. Timer 2 has a capture feature in which the value

of the timer can be captured in two 8-bit registers upon the

assertion of an external input signal (see the Timers section).

Serial Port SFRs

The two full-duplex serial port peripherals each require two

registers, one for setting up the baud rate and other communication

parameters, and another byte for the transmit/receive buffer. The

ADE5166/ADE5169 also provide enhanced serial port function-

ality with a dedicated timer for baud rate generation with a

fractional divisor and additional error detection (see the UART

Serial Interface section and the UART2 Serial Interface section.)

Interrupt SFR

There is a two-tiered interrupt system standard in the 8052

core. The priority level for each interrupt source is individually

selectable as high or low. TheADE5166/ADE5169 enhance this

interrupt system by creating, in essence, a third interrupt tier

for a highest priority power supply management interrupt, PSM

(see the Interrupt System section).

I/O Port SFRs

The 8052 core supports four I/O ports, P0 through P3, where

Port 0 and Port 2 are typically used for access to external code

and data spaces. The ADE5166/ADE5169, unlike standard 8052

products, provide internal nonvolatile flash memory so that an

external code space is unnecessary. The on-chip LCD driver

requires many pins, some of which are dedicated for LCD

functionality and others that can be configured at LCD or

general-purpose I/O. Due to the limited number of I/O pins,

the ADE5166/ADE5169 do not allow access to external code

and data spaces.

The ADE5166/ADE5169 provide 20 pins that can be used for

general-purpose I/O. These pins are mapped to Port 0, Port 1, and

Port 2 and are accessed through three bit-addressable 8052 SFRs:

P0, P1, and P2. Another enhanced feature of the ADE5166/

ADE5169 is that the weak pull-ups standard on 8052 Port 1,

Port 2, and Port 3 can be disabled to make open-drain outputs,

as is standard on Port 0. The weak pull-ups can be enabled on

a pin-by-pin basis (see the I/O Ports section).

Power Control Register (PCON, Address 0x87)

The 8052 core defines two power-down modes: power-down

and idle. The ADE5166/ADE5169 enhance the power control

capability of the traditional 8052 MCU with additional power

management functions. The POWCON register is used to

define power control specific functionality for the ADE5166/

ADE5169. The program control SFR (PCON, Address 0x87) is

not bit addressable (see

the Power Management section).

The ADE5166/ADE5169 provide many other peripherals not

standard to the 8052 core, for example

•

ADE energy measurement DSP

•

Full RTC

•

LCD driver

•

Battery switchover/power management

•

Temperature ADC

•

Battery ADC

•

SPI/I2C communication

•

Flash memory controller

•

Watchdog timer

•

Secondary UART port

MEMORY OVERVIEW

The ADE5166/ADE5169 contain three memory blocks.

•

62 kB of on-chip Flash/EE program and data memory

•

256 bytes of general-purpose RAM

•

2 kB of internal extended RAM (XRAM)

The 256 bytes of general-purpose RAM share the upper 128 bytes

of its address space with the SFRs. All of the memory spaces are

shown in Figure 76. The addressing mode specifies which

memory space to access.

ADE5166 数据表(PDF) 77 Page - Analog Devices

ADE5166 数据表(HTML) 77 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载