ADE5166 datasheet(46/148 Pages) AD

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ADE5166/ADE5169

Rev. 0 | Page 46 of 148

FAULT DETECTION

The ADE5166/ADE5169 incorporate a fault detection scheme

that warns of fault conditions and allows accurate measurement

to continue during a fault event. The ADE5166/ADE5169 do

this by continuously monitoring both current inputs (IPA and IPB).

For ease of understanding, these currents are referred to as phase

and neutral (return) currents. In the ADE5166/ADE5169, a fault

condition is defined when the difference between IPA and IPB is

greater than 6.25% of the active channel. If a fault condition is

detected and the inactive channel is larger than the active channel,

the ADE5166/ADE5169 automatically switch current measure-

ment to the inactive channel. During a fault, the active, reactive,

and apparent power and the Irms are generated using the larger of

the two currents. On power-up, IPA is the current input selected

for active, reactive, and apparent power and IRMS calculations.

To prevent a false alarm, averaging is done for the fault detection,

and a fault condition is detected approximately one second after

the event. The fault detection is automatically disabled when the

voltage signal is less than 0.3% of the full-scale input range. This

eliminates false detection of a fault due to noise at light loads.

Because the ADE5166/ADE5169 look for a difference between

the voltage signals on IPA and IPB, it is important that both current

transducers be closely matched.

Channel Selection Indication

The current channel selected for measurement is indicated by

Bit 7 (ICHANNEL) in the ACCMODE register (Address 0x0F).

When this bit is cleared, IPA is selected and, when it is set, IPB is

selected. The ADE5166/ADE5169 automatically switch from one

channel to the other and report the channel configuration in the

ACCMODE register.

The current channel selected for measurement can also be forced.

Setting the SEL_I_CH[5:4] bits in the CALMODE register

(Address 0x3D) selects IPA and IPB, respectively. When both bits

are cleared or set, the current channel used for measurement is

selected automatically based on the fault detection.

Fault Indication

The ADE5166/ADE5169 provide an indication of the part going

in or out of a fault condition. The new fault condition is indicated

by the FAULTSIGN flag (Bit 5) in the Interrupt Status 1 SFR

(MIRQSTL, Address 0xDC).

When the FAULTSIGN bit (Bit 6) of the ACCMODE register

(Address 0x0F) is cleared, the FAULTSIGN flag in the Interrupt

Status 1 SFR (MIRQSTL, Address 0xDC) is set when the part is

entering a fault condition or a normal condition.

When the FAULTSIGN bit (Bit 5) is set in the Interrupt Enable 1

SFR (MIRQENL, Address 0xD9), and the FAULTSIGN flag

(Bit 5) in the Interrupt Status 1 SFR (MIRQSTL, Address 0xDC)

is set, the 8052 core has a pending ADE interrupt.

Fault with Active Input Greater Than Inactive Input

If IPA is the active current input (that is, being used for billing),

and the voltage signal on IPB (inactive input) falls below 93.75%

of IPA, and the FAULTSIGN bit (Bit 6) of the ACCMODE register

(Address 0x0F) is cleared, the FAULTSIGN flag (Bit 5) in the

Interrupt Status 1 SFR (MIRQSTL, Address 0xDC) is set. Both

analog inputs are filtered and averaged to prevent false

triggering of this logic output. As a consequence of the filtering,

there is a time delay of approximately 3 sec on the logic output

after the fault event. The FAULTSIGN flag is independent of

any activity. Because IPA is the active input and it is still greater

than IPB, billing is maintained on IPA; that is, no swap to the IPB

input occurs. IPA remains the active input.

Fault with Inactive Input Greater Than Active Input

If the difference between IPB, the inactive input, and IPA, the active

input (that is, being used for billing), becomes greater than 6.25%

of IPB, and the FAULTSIGN bit (Bit 6) of the ACCMODE register

(Address 0x0F) is cleared, the FAULTSIGN flag (Bit 5)in the

Interrupt Status 1 SFR (MIRQSTL, Address 0xDC) is set. The

IPB analog input becomes the active input. Again, a time constant

of about 3 sec is associated with this swap. IPA does not swap back

to the active channel until IPA is greater than IPB and the difference

between IPA and IPB, in this order, becomes greater than 6.25% of

IPB. However, if the FAULTSIGN bit (Bit 6) of the ACCMODE

Interrupt Status 1 SFR (MIRQSTL, Address 0xDC) is set as soon

as IPA is within 6.25% of IPB. This threshold eliminates concerns

about potential chatter between IPA and IPB calibration.

Typically, when a meter is calibrated, the voltage and current

circuits are separated, as shown in Figure 45. Current passes

through only the phase circuit or the neutral circuit. Figure 45

shows current being passed through the phase circuit. This is the

preferred option because the ADE5166/ADE5169 start billing on

the IPA input on power-up. The phase circuit CT is connected to

IPA in the diagram. Because the current sensors are not perfectly

matched, it is important to match current inputs. The ADE5166/

ADE5169 provide a gain calibration register for IPB, IBGAIN

(Address 0x1C). IBGAIN is a 12-bit, signed, twos complement

AGND

IPA

IPB

TEST

CURRENT

240V rms

Figure 45. Fault Conditions for Inactive Input Greater Than Active Input

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