ADE5166 datasheet(27/148 Pages) AD

27 / 148 page

ADE5166/ADE5169

Rev. 0 | Page 27 of 148

POWER SUPPLY ARCHITECTURE

The ADE5166/ADE5169 have two power supply inputs, VDD and

VBAT, and they require only a single 3.3 V power supply at VDD for

full operation. A battery backup, or secondary power supply, with

a maximum of 3.7 V can be connected to the VBAT input. Internally,

the ADE5166/ADE5169 connect VDD or VBAT to VSWOUT, which is

used to derive power for the ADE5166/ADE5169 circuitry. The

VSWOUT output pin reflects the voltage at the internal power supply

(VSWOUT) and has a maximum output current of 6 mA. This pin

can also be used to power a limited number of peripheral compo-

nents. The 2.5 V analog supply (VINTA) and the 2.5 V supply for

the core logic (VINTD) are derived by on-chip linear regulators from

VSWOUT. Figure 30 shows the ADE5166/ADE5169 power supply

architecture.

The ADE5166/ADE5169 provide automatic battery switchover

between VDD and VBAT based on the voltage level detected at VDD

or VDCIN. In addition, the BCTRL input can be used to trigger a

battery switchover. The conditions for switching VSWOUT from VDD

to VBAT and back to VDD are described in the Battery Switchover

section. VDCIN is an input pin that can be connected to a 0 V to

3.3 V dc signal. This input is intended for power supply super-

visory purposes and does not provide power to the ADE5166/

ADE5169 circuitry (see the Battery Switchover section).

POWER SUPPLY

MANAGEMENT

LDO

VINTD

LDO

VINTA

ADC

VSW

ADC

MCU

ADE

SPI/I2C

VDCIN VDD VBAT

VSWOUT

BCTRL

SCRATCH PAD

LCD

RTC

TEMPERATURE ADC

3.3V

UART

2.5V

Figure 30. Power Supply Architecture

BATTERY SWITCHOVER

The ADE5166/ADE5169 monitor VDD, VBAT, and VDCIN. Auto-

matic battery switchover from VDD to VBAT can be configured

based on the status of the VDD, the VDCIN, or the BCTRL pin. Battery

switchover is enabled by default. Setting Bit 1 in the battery

switchover configuration SFR (BATPR, Address 0xF5) disables

battery switchover so that VDD is always connected to VSWOUT (see

Table 18). The source of VSWOUT is indicated by Bit 6 in the

peripheral configuration SFR (PERIPH, Address 0xF4), which is

described in Table 19. Bit 6 is set when VSWOUT is connected to

VDD and cleared when VSWOUT is connected to VBAT.

The battery switchover functionality provided by the ADE5166/

ADE5169 allows a seamless transition from VDD to VBAT. An auto-

matic battery switchover option ensures a stable power supply to

the ADE5166/ADE5169, as long as the external battery voltage

is above 2.75 V. It allows continuous code execution even while

the internal power supply is switching from VDD to VBAT and back.

Note that the energy metering ADCs are not available when

VBAT is being used for VSWOUT.

Power supply management (PSM) interrupts can be enabled to

indicate when battery switchover occurs and when the VDD

power supply is restored (see the Power Supply Management

(PSM) Interrupt section.)

VDD to VBAT

The following three events switch the internal power supply

(VSWOUT) from VDD to VBAT:

•

VDCIN < 1.2 V. When VDCIN falls below 1.2 V, VSWOUT switches

from VDD to VBAT. This event is enabled when the

BATPRG[1:0] bits in the battery switchover configuration

SFR (BATPR, Address 0xF5) = 0b01.

•

VDD < 2.75 V. When VDD falls below 2.75 V, VSWOUT switches

from VDD to VBAT. This event is enabled when BATPRG[1:0] in

the BATPR SFR are cleared.

•

Falling edge on BCTRL. When the battery control pin,

BCTRL, goes low, VSWOUT switches from VDD to VBAT. This

external switchover signal can trigger a switchover to VBAT

at any time. Setting the INT1PRG bits to 0bx01 in the inter-

rupt pins configuration SFR (INTPR, Address 0xFF) enables

the battery control pin (see Table 16).

Switching from VBAT to VDD

To switch VSWOUT from VBAT to VDD, all of the following events

must be true:

•

VDD > 2.75 V. VSWOUT switches back to VDD after VDD remains

above 2.75 V.

•

VDCIN > 1.2 V and VDD > 2.75 V. If the low VDCIN condition

is enabled, VSWOUT switches to VDD after VDCIN remains

above 1.2 V and VDD remains above 2.75 V.

•

Rising edge on BCTRL. If the battery control pin is enabled,

VSWOUT switches back to VDD after BCTRL is high, and the

first or second bullet point is satisfied.

POWER SUPPLY MANAGEMENT (PSM) INTERRUPT

The power supply management (PSM) interrupt alerts the 8052

core of power supply events. The PSM interrupt is disabled by

default. Setting the EPSM bit in the interrupt enable and Priority 2

SFR (IEIP2, Address 0xA9) enables the PSM interrupt (see

Table 82).

The power management interrupt enable SFR (IPSME,

Address 0xEC) controls the events that result in a PSM interrupt

(see Table 20).

Figure 31 illustrates how the PSM interrupt vector is shared among

the PSM interrupt sources. The PSM interrupt flags are latched

and must be cleared by writing to the IPSMF power management

interrupt flag SFR, Address 0xF8 (see Table 17).

ADE5166 数据表(PDF) 27 Page - Analog Devices

ADE5166 数据表(HTML) 27 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载