ADE5166 datasheet(112/148 Pages) AD

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ADE5166/ADE5169

Rev. 0 | Page 112 of 148

REAL-TIME CLOCK (RTC)

The ADE5166/ADE5169 have an embedded RTC (see Figure 98).

The external 32.768 kHz crystal is used as the clock source for

the RTC. Calibration is provided to compensate the nominal

crystal frequency and for variations in the external crystal fre-

quency over temperature. By default, the RTC is active in all the

power saving modes. The RTC counters retain their values

through watchdog resets and external resets and are reset only

during a power-on reset.

The ADE5166/ADE5169 provide two ways to access the RTC

data: by direct access through SFRs for configuration and by

indirect access through address and data SFRs for the timekeeping

registers and some other configurations. The address and data

SFRs act as pointers to the RTC internal registers.

ACCESS TO RTC SFRs

Access to the RTC SFRs is achieved by reading or writing to the

SFR addresses that are detailed in the Access to Internal RTC

Registers section. Writing to the indirect registers is protected

by a key, as explained in the Writing to Internal RTC Registers

section. Reading is not protected.

ACCESS TO INTERNAL RTC REGISTERS

Access to the internal RTC measurement registers is achieved by

writing to the RTC pointer address SFR (RTCPTR, Address 0xA3).

The RTCPTR register selects the RTC register to be accessed

and determines if a read or a write is performed (see Table 129).

Writing to Internal RTC Registers

The RTC circuitry runs off a 32.768 kHz clock. The timekeeping

registers, HTHSEC, SEC, MIN, HOUR, DAY, DATE, MONTH,

and YEAR are updated with a 32.768 kHz clock. However, the

TIMECON (Address 0xA1) and TIMECON2 (Address 0xA2)

SFRs and the INTVAL register (Address 0x09) are updated with

a 128 Hz clock. It takes up to two 128 Hz clock cycles from when

the MCU writes the TIMECON, TIMECON2, or INTVAL SFRs

until they are successfully updated in the RTC.

When the RTCW_RB bit of the RTCPTR SFR (Address 0xA3)

is set, the content of the RTCDAT SFR (Address 0xA4) is

transferred to the internal RTC register designated by the

address in the RTCPTR SFR. To protect the RTC timekeeping

registers from runaway code, a key must be written to the

KYREG SFR (Address 0xC1) to obtain write access to any of the

RTC indirect registers. The KYREG should be set to 0xEA to

unlock the timekeeping registers and is reset to zero after a

timekeeping register is written.

The RTC registers can be written using the following 8052

assembly code:

MOV

RTCKey, #0EAh

CALL

UpdateRTC

…

UpdateRTC:

MOV

KYREG, RTCKey

MOV

RTCDAT, #30

MOV

RTCPTR, #82h

MOV

KYREG, RTCKey

MOV

RTCDAT, #05

MOV

RTCPTR, #83h

MOV

KYREG, RTCKey

MOV

RTCDAT, #04

MOV

RTCPTR, #84h

MOV

RTCKey, #00h

RET

Reading Internal Energy Measurement Registers

When Bit 7 of the RTCPTR SFR is cleared, the content of the

internal RTC data register designated by the address in RTCPTR

is transferred to the RTCDAT SFR. The RTC cannot be stopped

to read the current time because stopping the RTC introduces

an error in its timekeeping. Therefore, the RTC is read on-the-fly,

and the counter registers must be checked for overflow. This

can be accomplished using the following 8052 assembly code:

ReadAgain:

MOV

RTCPTR #01

; Read HTHSEC using Bank

MOV

R0, RTCDAT

MOV

RTCPTR, #02

; Read SEC

MOV

R1, RTCDAT

MOV

RTCPTR, #03

; Read MIN

MOV

R2, RTCDAT

MOV

RTCPTR, #04

; Read HOUR

MOV

R3, RTCDAT

MOV

RTCPTR, #01

; Read HTHSEC

MOV

A, RTCDAT

CJNE

A, 00h, ReadAgain

; 00h is R0 in

Bank 0

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