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ADE5166 数据表(PDF) 128 Page - Analog Devices |
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ADE5166 数据表(HTML) 128 Page - Analog Devices |
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128 / 148 page  ADE5166/ADE5169 Rev. 0 | Page 128 of 148 Bit Mnemonic Default Description [2:0] DIV2 0 Binary divider. DIV2 Result 000 Divide by 1 (see Table 144) 001 Divide by 2 (see Table 144) 010 Divide by 4 (see Table 144) 011 Divide by 8 (see Table 144) 100 Divide by 16 (see Table 144) 101 Divide by 32 (see Table 144) 110 Divide by 164 (see Table 144) 111 Divide by 128 (see Table 144) Table 149. Common Baud Rates Using the UART2 Timer with a 4.096 MHz PLL Clock Ideal Baud CD SBTH2 DIV2 SBAUDT SBF2 SBAUDF2 % Error 115,200 0 0 1 0x01 0 0x07 + 0.16 115,200 1 0 0 0x00 0 0x07 + 0.16 57,600 0 0 2 0x02 0 0x07 + 0.16 57,600 1 0 1 0x01 0 0x07 + 0.16 38,400 0 0 2 0x02 1 0x2B −0.31 38,400 1 0 1 0x01 1 0x2B −0.31 38,400 2 0 0 0x00 1 0x2B −0.31 19,200 0 0 3 0x03 1 0x2B −0.31 19,200 1 0 2 0x02 1 0x2B −0.31 19,200 2 0 1 0x01 1 0x2B −0.31 19,200 3 0 0 0x00 1 0x2B −0.31 9600 0 0 4 0x04 1 0x2B −0.31 9600 1 0 3 0x03 1 0x2B −0.31 9600 2 0 2 0x02 1 0x2B −0.31 9600 3 0 1 0x01 1 0x2B −0.31 9600 4 0 0 0x00 1 0x2B −0.31 4800 0 0 5 0x05 1 0x2B −0.31 4800 1 0 4 0x04 1 0x2B −0.31 4800 2 0 3 0x03 1 0x2B −0.31 4800 3 0 2 0x02 1 0x2B −0.31 4800 4 0 1 0x01 1 0x2B −0.31 4800 5 0 0 0x00 1 0x2B −0.31 2400 0 0 6 0x06 1 0x2B −0.31 2400 1 0 5 0x05 1 0x2B −0.31 2400 2 0 4 0x04 1 0x2B −0.31 2400 3 0 3 0x03 1 0x2B −0.31 2400 4 0 2 0x02 1 0x2B −0.31 2400 5 0 1 0x01 1 0x2B −0.31 2400 6 0 0 0x00 1 0x2B −0.31 300 0 2 7 0x17 1 0x2B −0.31 300 1 1 7 0x0F 1 0x2B −0.31 300 2 0 7 0x07 1 0x2B −0.31 300 3 0 6 0x06 1 0x2B −0.31 300 4 0 5 0x05 1 0x2B −0.31 300 5 0 4 0x04 1 0x2B −0.31 300 6 0 3 0x03 1 0x2B −0.31 300 7 0 2 0x02 1 0x2B −0.31 |
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