ADE5166 datasheet(136/148 Pages) AD

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ADE5166/ADE5169

Rev. 0 | Page 136 of 148

SPITx

SPI INTERRUPT AND STATUS FLAGS

The SPI interface has several status flags that indicate the status

of the double-buffered receive and transmit registers. Figure 107

shows when the status and interrupt flags are raised. The transmit

interrupt occurs when the transmit shift register is loaded with the

data in the SPI/I2C transmit buffer SFR (SPI2CTx, Address 0x9A)

SPI/I2C transmit buffer SFR (SPI2CTx, Address 0x9A) register

has not been written with new data by the beginning of the next

byte transfer, the transmit operation stops.

When a new byte of data is received in the SPI/I2C receive buffer

SFR (SPI2CRx, Address 0x9B), the SPI receive interrupt flag is

raised. If the data in the SPI/I2C receive buffer SFR (SPI2CRx,

Address 0x9B) is not read before new data is ready to be loaded

into the SPI/I2C receive buffer SFR (SPI2CRx, Address0x9B),

an overflow condition has occurred. This overflow condition,

indicated by the SPIRxOF flag, forces the new data to be discarded

or overwritten if the RxOFW bit (SPIMOD1, Address 0xE8) is set.

TRANSMIT SHIFT REGISTER

SPITxIRQ = 1

SPITx (EMPTY)

TRANSMIT SHIFT REGISTER

STOPS TRANSFER IF TIMODE = 1

SPIRx

RECEIVE SHIFT REGISTER

SPIRxIRQ = 1

SPIRx (FULL)

RECEIVE SHIFT REGISTER

SPIRxOF = 1

Figure 107. SPI Receive and Transmit Interrupt and Status Flags

SCLK

(SPICPOL = 1)

SCLK

(SPICPOL = 0)

MISO

MOSI

SPIRx AND

SPITx FLAGS

WITH INTMOD = 1

SPIRx AND

SPITx FLAGS

WITH INTMOD = 0

SPIRx AND

SPITx FLAGS

WITH INTMOD = 0

SPICPHA = 1

MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB

MISO

MOSI

SPIRx AND

SPITx FLAGS

WITH INTMOD = 1

SPICPHA = 0

Figure 108. SPI Timing Configurations

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