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ST72371 数据表(PDF) 17 Page - STMicroelectronics |
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ST72371 数据表(HTML) 17 Page - STMicroelectronics |
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17 / 94 page ![]() 17/94 ST72371/ST72372 RESET (Cont’d) Table 6. List of sections affected by RESET, WAIT and HALT (Refer to 3.6 for Wait and Halt Modes) Figure 11. Reset Timing Diagram Note: Refer to Electrical Characteristics for values of tDDR and tOXOV Section RESET WAIT HALT CPU clock running at 4 MHz X Timer Prescaler reset to zero X Timer Counter set to FFFCh X All Timer enable bits set to 0 (disabled) X Data Direction Registers set to 0 (as Inputs) X Set Stack Pointer to 01FFh X Force Internal Address Bus to restart vector FFFEh, FFFFh X Set Interrupt Mask Bit (I-Bit, CC) to 1 (Interrupt disable) X Set Interrupt Mask Bit (I-Bit, CC) to 0 (Interrupt enable) X X Reset HALT latch X Reset WAIT latch X Disable Oscillator (for 4096 cycles) X X Set Timer Clock to 0 X X Watchdog counter reset X Watchdog register reset X Port data registers reset X Other on-chip peripherals: registers reset X VDD OSCIN fCPU FFFF FFFE PC RESET WATCHDOG RESET tDDR tOXOV 4096 CPU CLOCK CYCLES DELAY |
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