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ST72371/ST72372

4.4 I C BUS INTERFACE (I2C)

4.4.1 Introduction

The I

2C Bus Interface serves as an interface be-

tween the microcontroller and the serial I2C bus. It

provides both multimaster and slave functions,

and controls all I

2C bus-specific sequencing, pro-

tocol, arbitration and timing. It supports fast I C

mode (400kHz).

4.4.2 Main Features

– Parallel bus /I

2C protocol converter

– Multi-Master capability

– Interrupt generation

– Standard I

2C mode/Fast I2C mode

– 7-bit Addressing

2C Slave Mode

– Start bit detection flag

– Detection of misplaced Start or Stop condition

– Transfer problem detection

– Address Matched detection

– Default Address detection

– End of byte transmission flag

– Transmitter /Receiver flag

– Stop bit Detection

I2C Master Mode

–I

2C bus busy flag

– Arbitration lost flag

– End of byte transmission flag

– Transmitter /Receiver flag

– Clock generation

4.4.3 General Description

In addition to receiving and transmitting data, this

interface converts it from serial to parallel format

and vice versa, using either an interrupt or polled

handshake. The interrupts are enabled or disabled

by software. The interface is connected to the I2C

bus by a data pin (SDAI) and by a clock pin (SCLI).

It can be connected both with a standard I

2Cbus

and a Fast I

2C bus. This selection is made by soft-

ware.

Mode Selection

The interface can operate in the four following mo-

des:

– Slave transmitter/receiver

– Master transmitter/receiver

By default, it operates in slave mode.

The interface automatically switches from slave to

master after it generates a START condition and

from master to slave in case of arbitration loss or a

STOP generation, this allows Multi-Master capabi-

lity.

Communication Flow

In Master mode, it initiates a data transfer and ge-

nerates the clock signal. A serial data transfer

always begins with a start condition and ends with

a stop condition. Both start and stop conditions are

generated in master mode by software.

In Slave mode, the interface is capable of recogni-

sing its own address (7-bit), and the General Call

address. The General Call address detection may

be enabled or disabled by software.

Data and addresses are transferred as 8-bit bytes,

MSB first. The first byte following the start condi-

tion is the address byte; it is always transmitted in

Master mode.

A 9th clock pulse follows the 8 clock cycles of a

byte transfer, during which the receiver must send

an acknowledge bit to the transmitter. Refer toFig-

ure 1.

Figure 1. I

2C BUS Protocol

SCL

SDA

MSB

ACK

STOP

START

CONDITION

VR02119B

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