ST72371 datasheet(48/94 Pages) STMICROELECTRONICS

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ST72371/ST72372

I C BUS INTERFACE (Cont’d)

Acknowledge may be enabled and disabled by

software.

The I2C interface address and/or general call ad-

dress can be selected by software.

The speed of the I2C interface may be selected

between Standard (0-100KHz) and Fast I2C (100-

400KHz).

SDA/SCL Line Control

Transmitter mode: the interface holds the clock

line low before transmission to wait for the micro-

controller to write the byte in the Data Register.

Receiver mode: the interface holds the clock line

low after reception to wait for the microcontroller to

read the byte in the Data Register.

The SCL frequency (FSCL) is controlled by a pro-

grammable clock divider which depends on the

2C bus mode.

When the I

2C cell is enabled, the SDA and SCL

ports must be configured as floating open-drain

output or floating input. In this case, the value of

the external pull-up resistance used depends on

the application.

When the I2C cell is disabled, the SDA and SCL

ports revert to being standard I/ O port pins.

Figure 2. I

2C Interface Block Diagram

DATA REGIST ER (DR)

DATA SHIFT REGISTER

COMPARATOR

OWN ADDRES S REGISTE R (OAR)

CLOCK CONTROL REGISTER (CCR)

STA TUS REGISTER 1 (SR1)

CONTROL REGISTER (CR)

SDAI

SCLI

CONTROL LOGIC

STA TUS REGISTER 2 (SR2)

INTERRU PT

CLOCK CONTROL

DATA CONTROL

SCL

SDA

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