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ST72371 数据表(PDF) 27 Page - STMicroelectronics |
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ST72371 数据表(HTML) 27 Page - STMicroelectronics |
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27 / 94 page  27/94 ST72371/ST72372 I/O PORTS (Cont’d) 4.1.2.6 Device Specific Configurations Table 9. ST72372N Port Configuration *Reset state. Table 10. ST72372J Port Configuration *Reset state. Note: The DA1-DA4 output pins are configurable as push pull or open drain using the POC0 Bit in the Mis- cellaneous Register. Port Pin name Input (DDR=0) Output (DDR=1) OR=0* OR=1 OR=0 OR=1 Port A PA0:PA7 floating true open drain, high sink capability Port B PB0:PB7 pull-up floating (for analog conversion only) push-pull Port C PC0:PC1 pull-up push-pull PC2:PC5 floating open drain PC6 pull-up true open drain, high sink capability PC7 pull-up push-pull Port D PD0:PD7 pull-up push-pull Port Pin name Input (DDR=0) Output (DDR=1) OR=0* OR=1 OR=0 OR=1 Port A PA1, PA3:7 floating true open drain, high sink capability Port B PB0:2, PB7 pull-up floating (for analog conversion only) push-pull Port C PC0 pull-up push-pull PC2:PC5 floating open drain PC6 pull-up push-pull Port D PD0:PD6 pull-up push-pull |
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