EP1M350 datasheet(57/86 Pages) ALTERA

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Altera Corporation

Mercury Programmable Logic Device Family Data Sheet

Table 12 describes the I/O standards supported by Mercury devices.

Each regular I/O band row contains two I/O banks. The number of I/O

banks in a Mercury device depends on the number of I/O band rows. The

top I/O band contains four regular I/O banks specifically designed for

HSDI. The top I/O band banks and dedicated clock inputs support LVDS,

LVPECL, and 3.3-V PCML. 3.3-V PCML is an open-drain standard and

therefore requires external termination to 3.3 V. All other standards are

supported by all I/O banks. The top I/O banks 1, 2, 3, and 4 only support

non-HSDI I/O pins if the design does not use HSDI circuitry. If the design

uses any HSDI channel, banks 1, 2, 3, and 4 all do not support regular I/O

pins.

Additionally, the EP1M350 device includes the Flexible-LVDS feature,

providing support for up to 100 LVDS channels on all regular I/O banks.

Regular I/O banks in EP1M350 devices include dedicated LVDS input

and output buffers that do not require any external components except for

100-

Ω termination resistors on receiver channels.

Table 12. Mercury Supported I/O Standards

I/O Standard

Type

Input

Reference

Voltage (VREF)

(V)

Output

Supply

Voltage

(VCCIO) (V)

Board

Termination

Voltage

(VTT) (V)

LVTTL

Single-ended

N/A

3.3

N/A

LVCMOS

Single-ended

N/A

3.3

N/A

2.5 V

Single-ended

N/A

2.5

N/A

1.8 V

Single-ended

N/A

1.8

N/A

3.3-V PCI

Single-ended

N/A

3.3

N/A

3.3-V PCI-X

Single-ended

N/A

3.3

N/A

LVDS

Differential

N/A

3.3

N/A

LVPECL

Differential

N/A

3.3

N/A

3.3-V PCML

Differential

N/A

3.3

GTL+

Voltage referenced

1.0

N/A

1.5

HSTL class I and II

Voltage referenced

0.75

1.5

0.75

SSTL-2 class I and II

Voltage referenced

1.25

2.5

1.25

SSTL-3 class I and II

Voltage referenced

1.5

3.3

1.5

AGP

Voltage referenced

1.32

3.3

N/A

CTT

Voltage referenced

1.5

3.3

1.5

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