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EP1M350 数据表(PDF) 83 Page - Altera Corporation

部件名 EP1M350
功能描述  Programmable Logic Device Family
PDF  86 Pages
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制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
标志 ALTERA - Altera Corporation

EP1M350 数据表(HTML) 83 Page - Altera Corporation

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Altera Corporation
83
Mercury Programmable Logic Device Family Data Sheet
13
Notes to Tables 46 – 51:
(1)
Timing will vary by I/O pin placement. Therefore, use the Quartus II software to determine exact I/O timing for
each pin.
(2)
This parameter is measured with the Increase tZX Delay to Output Pin option set to Off.
(3)
This parameter is measured with the Increase tZX Delay to Output Pin option set to On.
Power
Consumption
Detailed power consumption information for Mercury devices will be
released when available.
Configuration &
Operation
The Mercury architecture supports several configuration schemes. This
section summarizes the device operating modes and available device
configuration schemes.
Operating Modes
The Mercury architecture uses SRAM configuration elements that require
configuration data to be loaded each time the circuit powers up. The
process of physically loading the SRAM data into the device is called
configuration. During initialization, which occurs immediately after
configuration, the device resets registers, enables I/O pins, and begins to
operate as a logic device. The I/O pins are tri-stated during power-up and
before and during configuration. Together, the configuration and
initialization processes are called command mode; normal device
operation is called user mode.
Table 51. EP1M350 External Bidirectional Timing Parameters
Note (1)
Symbol
-5 Speed Grade
-6 Speed Grade
-7 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
tINSUBIDIR
0.60
0.57
0.71
ns
tINHBIDIR
0.00
0.00
0.00
ns
tOUTCOBIDIR
2.00
3.95
2.00
3.97
2.00
4.75
ns
tXZBIDIR
3.90
3.93
4.70
ns
tZXBIDIR (2)
3.90
3.93
4.70
ns
tZXBIDIR (3)
4.10
4.13
4.94
ns
tINSUBIDIRPLL
0.69
0.70
0.82
ns
tINHBIDIRPLL
0.00
0.00
0.00
ns
tOUTCOBIDIRPLL
0.50
2.23
0.50
2.23
0.50
2.69
ns
tXZBIDIRPLL
2.19
2.18
2.63
ns
tZXBIDIRPLL (2)
2.19
2.18
2.63
ns
tZXBIDIRPLL (3)
2.39
2.38
2.87
ns



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